SN74LVC1G373 Latch Datasheet

SN74LVC1G373 Datasheet, PDF, Equivalent


Part Number

SN74LVC1G373

Description

Single D-Type Latch

Manufacture

etcTI

Total Page 30 Pages
Datasheet
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SN74LVC1G373
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SN74LVC1G373
SCES528F – DECEMBER 2003 – REVISED MAY 2017
SN74LVC1G373 Single D-Type Latch With 3-State Output
1 Features
1 Available in the Texas Instruments
NanoFree™ Package
• Supports 5-V VCC Operation
• Inputs Accept Voltages to 5.5 V
• Provides Down Translation to VCC
• Max tpd of 4 ns at 3.3 V
• Low Power Consumption: 10-μA
Maximum ICC
• ±24-mA Output Drive at 3.3 V
• Ioff Supports Partial-Power-Down Mode and Back
Drive Protection
• Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II
2 Applications
• Servers
• Printers
• Telecom and Grid Infrastructure
• Memory Addressing
• Buffer Registers
• Electronic Point of Sale
3 Description
The SN74LVC1G373 device is a single D-type latch
designed for 1.65-V to 5.5-V VCC operation.
This device is particularly suitable for implementing
buffer registers, I/O ports, bidirectional bus drivers,
and working registers. While the latch-enable (LE)
input is high, the Q outputs follow the data (D) inputs.
When LE is taken low, the Q outputs are latched at
the logic levels set up at the D inputs.
NanoFree™ package technology is a major
breakthrough in IC packaging concepts, using the die
as the package.
OE does not affect the internal operations of the
latch. Old data can be retained or new data can be
entered while the outputs are in the high-impedance
state.
Device Information(1)
PACKAGE NUMBER
PACKAGE
BODY SIZE (NOM)
SN74LVC1G373DBV SOT-23 (6)
2.90 mm × 1.60 mm
SN74LVC1G373DCK SC70 (6)
2.00 mm × 1.25 mm
SN74LVC1G373YZP DSBGA (6)
1.41 mm × 0.91 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
6
OE
LE 1
3
D
C
D
4
Q
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

SN74LVC1G373
SN74LVC1G373
SCES528F – DECEMBER 2003 – REVISED MAY 2017
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information .................................................. 5
6.5 Electrical Characteristics........................................... 6
6.6 Timing Requirements: TA = –40°C to +85°C ............ 6
6.7 Timing Requirements: TA = –40°C to +125°C .......... 6
6.8 Switching Characteristics: TA = –40°C to +85°C ...... 7
6.9 Switching Characteristics: TA = –40°C to +85°C ...... 7
6.10 Switching Characteristics: TA = –40°C to +125°C .. 8
6.11 Operating Characteristics........................................ 8
6.12 Typical Characteristics ............................................ 9
7 Parameter Measurement Information ................ 10
8 Detailed Description ............................................ 12
8.1 Overview ................................................................. 12
8.2 Functional Block Diagram ....................................... 12
8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 13
9 Application and Implementation ........................ 14
9.1 Application Information............................................ 14
9.2 Typical Application .................................................. 14
10 Power Supply Recommendations ..................... 16
11 Layout................................................................... 16
11.1 Layout Guidelines ................................................. 16
11.2 Layout Example .................................................... 16
12 Device and Documentation Support ................. 17
12.1 Documentation Support ........................................ 17
12.2 Receiving Notification of Documentation Updates 17
12.3 Community Resource............................................ 17
12.4 Trademarks ........................................................... 17
12.5 Electrostatic Discharge Caution ............................ 17
12.6 Glossary ................................................................ 17
13 Mechanical, Packaging, and Orderable
Information ........................................................... 17
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (September 2016) to Revision F
Page
• Changed YZP Package pinout diagram and added YZP pin numbers in Pin Functions table .............................................. 3
• Added Balanced High-Drive CMOS Push-Pull Outputs, Standard CMOS Inputs, Clamp Diodes, Partial Power Down
(Ioff), Over-voltage Tolerant Inputs ........................................................................................................................................ 12
• Added Trace Example in Layout Example section............................................................................................................... 16
• Added Documentation Support section ................................................................................................................................ 17
Changes from Revision D (December 2013) to Revision E
Page
• Added Applications section, Device Information table, ESD Ratings table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ................................................................................................................................................................................... 1
Changes from Revision C (May 2007) to Revision D
Page
• Updated document to new TI data sheet format. ................................................................................................................... 1
• Deleted Ordering Information table; see POA at the end of the data sheet........................................................................... 1
• Updated operating temperature range. .................................................................................................................................. 5
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Copyright © 2003–2017, Texas Instruments Incorporated
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Features Product Folder Order Now Technical Doc uments Tools & Software Support & Com munity SN74LVC1G373 SCES528F – DECEM BER 2003 – REVISED MAY 2017 SN74LVC1G 373 Single D-Type Latch With 3-State Ou tput 1 Features •1 Available in the Texas Instruments NanoFree™ Package Supports 5-V VCC Operation • Input s Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max tpd of 4 ns at 3.3 V • Low Power Consumptio n: 10-μA Maximum ICC • ±24-mA Outpu t Drive at 3.3 V • Ioff Supports Part ial-Power-Down Mode and Back Drive Prot ection • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II 2 Applica tions • Servers • Printers • Tele com and Grid Infrastructure • Memory Addressing • Buffer Registers • Ele ctronic Point of Sale 3 Description Th e SN74LVC1G373 device is a single D-typ e latch designed for 1.65-V to 5.5-V VC C operation. This device is particularl y suitable for implementing buffer regi sters, I/O ports, bidirectional bus drivers, and working registers. While the latch-enable (LE) input.
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