SN74LVC1G3208 Gate Datasheet

SN74LVC1G3208 Datasheet, PDF, Equivalent


Part Number

SN74LVC1G3208

Description

Single 3-Input Positive OR-AND Gate

Manufacture

etcTI

Total Page 22 Pages
Datasheet
Download SN74LVC1G3208 Datasheet


SN74LVC1G3208
SN74LVC1G3208
www.ti.com
SCES605B – SEPTEMBER 2004 – REVISED DECEMBER 2013
Single 3-Input Positive OR-AND Gate
Check for Samples: SN74LVC1G3208
FEATURES
1
2 Available in the Texas Instruments NanoStar™
and NanoFree™ Packages
• Supports 5-V VCC Operation
• Inputs Accept Voltages to 5.5 V
• Provides Down Translation to VCC
• Max tpd of 5 ns at 3.3 V
• Low Power Consumption, 10-µA Max ICC
• ±24-mA Output Drive at 3.3 V
• Input Hysteresis Allows Slow Input Transition
and Better Switching Noise Immunity at the
Input (Vhys = 250 mV Typ @ 3.3 V)
• Can Be Used in Three Combinations:
– OR-AND Gate
– OR Gate
– AND Gate
• Ioff Supports Live Insertion, Partial-Power-
Down Mode, and Back-Drive Protection
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DESCRIPTION
This device is designed for 1.65-V to 5.5-V VCC
operation.
The SN74LVC1G3208 device is a single 3-input
positive OR-AND gate. It performs the Boolean
function Y = (A + B) C in positive logic.
By tying one input to GND or VCC, the
SN74LVC1G3208 device offers two more functions.
When C is tied to VCC, this device performs as a 2-
input OR gate (Y = A + B). When A is tied to GND,
the device works as a 2-input AND gate (Y = B C).
This device also works as a 2-input AND gate when
B is tied to GND (Y = A C).
NanoStar™ and NanoFree™ package technology is
a major breakthrough in IC packaging concepts,
using the die as the package.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow
through the device when it is powered down.
DBV PACKAGE
(TOP VIEW)
A1
6
GND
2
5
C
VCC
DCK PACKAGE
(TOP VIEW)
A 1 6C
GND 2 5 VCC
B 3 4Y
YEP OR YZP PACKAGE
(BOTTOM VIEW)
B 34 Y
GND 2 5 VCC
A 16 C
B3
4Y
See mechanical drawings for dimensions.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar, NanoFree are trademarks of Texas Instruments.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2013, Texas Instruments Incorporated

SN74LVC1G3208
SN74LVC1G3208
SCES605B – SEPTEMBER 2004 – REVISED DECEMBER 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Function Table(1)
INPUTS
OUTPUT
ABC
Y
HXH H
XHH H
XXL
L
LLH L
(1) X = Valid H or L
Logic Diagram (Positive Logic)
1
A
3
B
C6
4
Y
Function Selection Table
LOGIC FUNCTION
FIGURE
2-Input AND Gate
Figure 1
2-Input OR Gate
Figure 2
Y = (A + B) C
Figure 3
Logic Configurations
VCC
VCC
BA
YY
C
1 6C
C
A1
6C
25
25
B3
4Y
3 4Y
Figure 1. 2-Input AND Gate
VCC
A
B
Y
A1
6
25
B3
4Y
Figure 2. 2-Input OR Gate
2 Submit Documentation Feedback
Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: SN74LVC1G3208


Features SN74LVC1G3208 www.ti.com SCES605B – SEPTEMBER 2004 – REVISED DECEMBER 201 3 Single 3-Input Positive OR-AND Gate Check for Samples: SN74LVC1G3208 FEATU RES 1 •2 Available in the Texas Instr uments NanoStar™ and NanoFree™ Pack ages • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Pr ovides Down Translation to VCC • Max tpd of 5 ns at 3.3 V • Low Power Cons umption, 10-µA Max ICC • ±24-mA Out put Drive at 3.3 V • Input Hysteresis Allows Slow Input Transition and Bette r Switching Noise Immunity at the Input (Vhys = 250 mV Typ @ 3.3 V) • Can Be Used in Three Combinations: – OR-AND Gate – OR Gate – AND Gate • Ioff Supports Live Insertion, Partial-Power Down Mode, and Back-Drive Protection Latch-Up Performance Exceeds 100 mA P er JESD 78, Class II • ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Mode l (C101) DESCRIPTION This device is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC1G3208 device is .
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