SN54165 Registers Datasheet

SN54165 Datasheet, PDF, Equivalent


Part Number

SN54165

Description

Parallel-Load 8-Bit Shift Registers

Manufacture

etcTI

Total Page 23 Pages
Datasheet
Download SN54165 Datasheet


SN54165
The SN54165 and SN74165 devices
are obsolete and are no longer supplied.
SN54165, SN54LS165A, SN74165, SN74LS165A
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SDLS062D – OCTOBER 1976 – REVISED FEBRUARY 2002
D Complementary Outputs
D Direct Overriding Load (Data) Inputs
D Gated Clock Inputs
D Parallel-to-Serial Data Conversion
TYPE
’165
’LS165A
TYPICAL MAXIMUM
CLOCK FREQUENCY
26 MHz
35 MHz
TYPICAL
POWER DISSIPATION
210 mW
90 mW
description
The ’165 and ’LS165A are 8-bit serial shift
registers that shift the data in the direction of QA
toward QH when clocked. Parallel-in access to
each stage is made available by eight individual,
direct data inputs that are enabled by a low level
at the shift/load (SH/LD) input. These registers
also feature gated clock (CLK) inputs and
complementary outputs from the eighth bit. All
inputs are diode-clamped to minimize
transmission-line effects, thereby simplifying
system design.
Clocking is accomplished through a two-input
positive-NOR gate, permitting one input to be
used as a clock-inhibit function. Holding either of
the clock inputs high inhibits clocking, and holding
either clock input low with SH/LD high enables the
other clock input. Clock inhibit (CLK INH) should
be changed to the high level only while CLK is
high. Parallel loading is inhibited as long as SH/LD
is high. Data at the parallel inputs are loaded
directly into the register while SH/LD is low,
independently of the levels of CLK, CLK INH, or
serial (SER) inputs.
SN54165, SN54LS165A . . . J OR W PACKAGE
SN74165 . . . N PACKAGE
SN74LS165A . . . D, N, OR NS PACKAGE
(TOP VIEW)
SH/LD
CLK
E
F
G
H
QH
GND
1
2
3
4
5
6
7
8
16 VCC
15 CLK INH
14 D
13 C
12 B
11 A
10 SER
9 QH
SN54LS165A . . . FK PACKAGE
(TOP VIEW)
3 2 1 20 19
E4
18 D
F5
17 C
NC 6
16 NC
G7
15 B
H8
14 A
9 10 11 12 13
NC – No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1

SN54165
SN54165, SN54LS165A, SN74165, SN74LS165A
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SDLS062D OCTOBER 1976 REVISED FEBRUARY 2002
The SN54165 and SN74165 devices
are obsolete and are no longer supplied.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP N Tube
SN74LS165AN
SN74LS165AN
0°C to 70°C
SOIC D
Tube
Tape and reel
SN74LS165AD
SN74LS165ADR
LS165A
SOP NS Tape and reel SN74LS165ANSR
74LS165A
CDIP J
55°C to 125°C
CFP W
Tube
Tube
Tube
SN54LS165AJ
SNJ54LS165AJ
SNJ54LS165AW
SN54LS165AJ
SNJ54LS165AJ
SNJ54LS165AW
LCCC FK Tube
SNJ54LS165AFK
SNJ54LS165AFK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
SH/LD CLK INH CLK
L XX
H LL
H L
H L
H HX
SER
X
X
H
L
X
PARALLEL
A...H
a...h
X
X
X
X
INTERNAL
OUTPUTS
QA
a
QA0
H
L
QA0
QB
b
QB0
QAn
QAn
QB0
OUTPUT
QH
h
QH0
QGn
QGn
QH0
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265


Features The SN54165 and SN74165 devices are obso lete and are no longer supplied. SN541 65, SN54LS165A, SN74165, SN74LS165A PAR ALLEL-LOAD 8-BIT SHIFT REGISTERS SDLS06 2D – OCTOBER 1976 – REVISED FEBRUAR Y 2002 D Complementary Outputs D Direc t Overriding Load (Data) Inputs D Gated Clock Inputs D Parallel-to-Serial Data Conversion TYPE ’165 ’LS165A TYP ICAL MAXIMUM CLOCK FREQUENCY 26 MHz 35 MHz TYPICAL POWER DISSIPATION 210 mW 9 0 mW description The ’165 and ’LS 165A are 8-bit serial shift registers t hat shift the data in the direction of QA toward QH when clocked. Parallel-in access to each stage is made available by eight individual, direct data inputs that are enabled by a low level at the shift/load (SH/LD) input. These regist ers also feature gated clock (CLK) inpu ts and complementary outputs from the e ighth bit. All inputs are diode-clamped to minimize transmission-line effects, thereby simplifying system design. Clo cking is accomplished through a two-input positive-NOR gate, permitting one.
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