MPC5675K Microcontroller Datasheet

MPC5675K Datasheet, PDF, Equivalent


Part Number

MPC5675K

Description

Microcontroller

Manufacture

NXP

Total Page 30 Pages
Datasheet
Download MPC5675K Datasheet


MPC5675K
NXP Semiconductors
Data Sheet: Technical Data
Document Number: MPC5675K
Rev. 9, 08/2019
MPC5675K Microcontroller
Data Sheet
MPC5675K
MAPBGA–225
15 mm x 15 mm
QFN12
##_mm_x_##mm
1 Introduction
1.1 Document overview
This document provides electrical specifications, pin
assignments, and package diagrams for the MPC5675K series
of microcontroller units (MCUs).
1.2 Description
The MPC5675K microcontroller, a SafeAssure solution, is a
32-bit embedded controller designed for advanced driver
assistance systems with RADAR, CMOS imaging, LIDAR
and ultrasonic sensors, and multiple 3-phase motor control
applications as in hybrid electric vehicles (HEV) in
automotive and high temperature industrial applications.
A member of NXP Semiconductor’s MPC5500/5600 family,
it contains the Book E compliant Power Architecture
technology core with Variable Length Encoding (VLE). This
core complies with the Power Architecture embedded
category, and is 100 percent user mode compatible with the
original Power PCuser instruction set architecture (UISA).
It offers system performance up to four times that of its
MPC5561 predecessor, while bringing you the reliability and
familiarity of the proven Power Architecture technology.
A comprehensive suite of hardware and software
development tools is available to help simplify and speed
system design. Development support is available from
leading tools vendors providing compilers, debuggers and
simulation development environments.
SOT-343R
##_mm_x_##mm
473 MAPBGA
(19 x 19 mm)
PKG-TBD
TBD ## mm x ## mm
257 MAPBGA
(14 x 14 mm)
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 Device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.4 Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.5 Feature list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.6 Feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 Package pinouts and signal descriptions . . . . . . . . . . . . . . . . 17
2.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . 69
3.3 Recommended operating conditions . . . . . . . . . . . . . . 70
3.4 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . 72
3.5 Electromagnetic interference (EMI) characteristics . . . 73
3.6 Electrostatic discharge (ESD) characteristics. . . . . . . . 74
3.7 Static latch-up (LU). . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.8 Power Management Controller (PMC) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.9 Supply current characteristics . . . . . . . . . . . . . . . . . . . 76
3.10 Temperature sensor electrical characteristics . . . . . . . 77
3.11 Main oscillator electrical characteristics . . . . . . . . . . . . 77
3.12 FMPLL electrical characteristics. . . . . . . . . . . . . . . . . . 78
3.13 16 MHz RC oscillator electrical characteristics . . . . . . 79
3.14 ADC electrical characteristics. . . . . . . . . . . . . . . . . . . . 80
3.15 Flash memory electrical characteristics . . . . . . . . . . . . 85
3.16 SRAM memory electrical characteristics . . . . . . . . . . . 87
3.17 GP pads specifications . . . . . . . . . . . . . . . . . . . . . . . . . 87
3.18 PDI pads specifications . . . . . . . . . . . . . . . . . . . . . . . . 90
3.19 DRAM pad specifications . . . . . . . . . . . . . . . . . . . . . . . 93
3.20 RESET characteristics . . . . . . . . . . . . . . . . . . . . . . . . 100
3.21 Reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
3.22 Peripheral timing characteristics. . . . . . . . . . . . . . . . . 107
4 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
4.1 Package mechanical data. . . . . . . . . . . . . . . . . . . . . . 131
5 Orderable parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
6 Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
7 Document revision historys . . . . . . . . . . . . . . . . . . . . . . . . . 137
NXP reserves the right to change the proudction detail specifications as may be
required to permit improvements in the design of its products.

MPC5675K
Introduction
1.3 Device comparison
Table 1. MPC5675K family device comparison
CPU
Buses
XBAR
Memory
Modules
Features
MPC5673K
MPC5674K
MPC5675K
Type
2 × e200z7d (SoR1) in lock-step or decoupled operation
Architecture
Harvard
Execution speed
0–150 MHz (+2% FM) 0–180 MHz (+2% FM) 0–180 MHz (+2% FM)
Nominal platform
frequency (in 1:1, 1:2,
and 1:3 modes)
0–75 MHz (+2% FM) 0–90 MHz (+2% FM) 0–90 MHz (+2% FM)
MMU
64 entries (SoR)
Instruction set PPC
Yes
Instruction set VLE
Yes
Instruction cache
16 KB, 4-way with EDC (SoR)
Data cache
16 KB, 4-way with Parity (SoR)
MPU
Yes (SoR)
Core bus
32-bit address, 64-bit data
Internal periphery bus
32-bit address, 32-bit data
Master × slave ports
Yes (SoR)
Static RAM (SRAM)
Code flash memory
Data flash memory
256 KB (ECC)
1 MB2 (ECC)
384 KB (ECC)
1.5 MB2 (ECC)
64 KB2 (ECC)
512 KB (ECC)
2 MB2 (ECC)
Analog-to-Digital
Converter (ADC)
257 pin pkg: 4 × 12 bit (22 external channels)
473 pin pkg: 4 × 12 bit (up to 34 external channels)
CRC unit
2 (3 contexts each)
Cross Triggering Unit
(CTU)
Deserial Serial
Peripheral Interface
(DSPI)
2 modules
(3 chip selects)3
2 modules
3 modules4
Digital I/Os
DRAM Controller
(DRAMC)
No
16
Yes5
Enhanced Direct
Memory Access (eDMA)
2 modules, 32 channels each
eTimer
3 modules, 6 channels each
MPC5675K Microcontroller Data Sheet, Rev. 9
2 NXP Semiconductors


Features NXP Semiconductors Data Sheet: Technical Data Document Number: MPC5675K Rev. 9 , 08/2019 MPC5675K Microcontroller Dat a Sheet MPC5675K MAPBGA–225 15 mm x 15 mm QFN12 ##_mm_x_##mm 1 Introduct ion 1.1 Document overview This document provides electrical specifications, pi n assignments, and package diagrams for the MPC5675K series of microcontroller units (MCUs). 1.2 Description The MPC5 675K microcontroller, a SafeAssure solu tion, is a 32-bit embedded controller d esigned for advanced driver assistance systems with RADAR, CMOS imaging, LIDAR and ultrasonic sensors, and multiple 3 -phase motor control applications as in hybrid electric vehicles (HEV) in auto motive and high temperature industrial applications. A member of NXP Semicondu ctor’s MPC5500/5600 family, it contai ns the Book E compliant Power Architect ure technology core with Variable Le ngth Encoding (VLE). This core complies with the Power Architecture embedded c ategory, and is 100 percent user mode compatible with the original Po.
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