DRA726 Processor Datasheet

DRA726 Datasheet, PDF, Equivalent


Part Number

DRA726

Description

Infotainment Applications Processor

Manufacture

etcTI

Total Page 30 Pages
Datasheet
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DRA726
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DRA72
SPRS956F – MARCH 2016 – REVISED JUNE 2018
DRA72x Infotainment Applications Processor
Silicon Revision 2.0
1 Device Overview
1.1 Features
1
• Architecture Designed for Infotainment
Applications
• Video, Image, and Graphics Processing Support
– Full-HD Video (1920 × 1080p, 60 fps)
– Multiple Video Input and Video Output
– 2D and 3D Graphics
• Arm® Cortex®-A15 Microprocessor Subsystem
• C66x Floating-Point VLIW DSP
– Fully Object-Code Compatible With C67x and
C64x+
– Up to Thirty-two 16 × 16-Bit Fixed-Point
Multiplies per Cycle
• Up to 512KB of On-Chip L3 RAM
• Level 3 (L3) and Level 4 (L4) Interconnects
• DDR3/DDR3L Memory Interface (EMIF) Module
– Supports up to DDR3-1333 (667 MHz)
– Up to 2GB Across Single Chip Select
• Dual Arm® Cortex®-M4 Image Processing Units
(IPU)
• IVA-HD Subsystem
• Display Subsystem
– Display Controller With DMA Engine and up to
Three Pipelines
– HDMI™ Encoder: HDMI 1.4a and DVI 1.0
Compliant
• 2D-Graphics Accelerator (BB2D) Subsystem
– Vivante® GC320 Core
• Video Processing Engine (VPE)
• Single-Core PowerVR™ SGX544 3D GPU
• One Video Input Port (VIP) Module
– Support for up to Four Multiplexed Input Ports
• General-Purpose Memory Controller (GPMC)
• Enhanced Direct Memory Access (EDMA)
Controller
• 2-Port Gigabit Ethernet (GMAC)
– Up to Two External Ports
• Sixteen 32-Bit General-Purpose Timers
• 32-Bit MPU Watchdog Timer
• Six High-Speed Inter-Integrated Circuit (I2C) Ports
• HDQ™/ 1-Wire® Interface
• Ten Configurable UART/IrDA/CIR Modules
• Four Multichannel Serial Peripheral Interfaces
(McSPI)
• Quad SPI Interface (QSPI)
• Media Local Bus Subsystem (MLBSS)
• Real-Time Clock Subsystem (RTCSS)
• SATA Interface
• Eight Multichannel Audio Serial Port (McASP)
Modules
• SuperSpeed USB 3.0 Dual-Role Device
• High-Speed USB 2.0 Dual-Role Device
• High-Speed USB 2.0 On-The-Go
• Four MultiMedia Card/Secure Digital/Secure Digital
Input Output Interfaces ( MMC™/ SD®/SDIO)
• PCI Express® 3.0 Subsystems With Two 5-Gbps
Lanes
– One 2-lane Gen2-Compliant Port
– or Two 1-lane Gen2-Compliant Ports
• Dual Controller Area Network (DCAN) Modules
– CAN 2.0B Protocol
• MIPI® CSI-2 Camera Serial Interface
• Up to 215 General-Purpose I/O (GPIO) Pins
• Power, Reset, and Clock Management
• On-Chip Debug With CTools Technology
• 28-nm CMOS Technology
• 23 mm × 23 mm, 0.8-mm Pitch, 760-Pin BGA
(ABC)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

DRA726
DRA72
SPRS956F – MARCH 2016 – REVISED JUNE 2018
www.ti.com
1.2 Applications
• Human-Machine Interface (HMI)
• Navigation
• Digital and Analog Radio
• Rear Seat Entertainment
• Multimedia Playback
• AM/FM/RDS and Digital Radio Decoding
• ADAS and Jacinto 6 Integration
1.3 Description
DRA72x ("Jacinto 6 Eco") infotainment applications processors are developed on the same architecture as
Jacinto 6 devices to meet the intense processing needs of the modern infotainment-enabled automobile
experiences.
DRA72x devices offer upward scalability to DRA74x devices, while being pin-compatible across the family,
allowing Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly
implement innovative connectivity technologies, speech recognition, audio streaming, and more. Jacinto 6
and Jacinto 6 Eco devices bring high processing performance through the maximum flexibility of a fully
integrated mixed processor solution.
Programmability is provided by a single-core Arm Cortex-A15 RISC CPU with Neon™ extensions and a TI
C66x VLIW floating-point DSP core. The Arm processor lets developers keep control functions separate
from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the
system software.
Additionally, TI provides a complete set of development tools for the Arm, and DSP, including C compilers
and a debugging interface for visibility into source code execution.
The DRA72x Jacinto 6 Eco processor family is qualified according to the AEC-Q100 standard.
DRA72x
PART NUMBER
Device Information
PACKAGE
FCBGA (760)
BODY SIZE
23.0 mm × 23.0 mm
2 Device Overview
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Copyright © 2016–2018, Texas Instruments Incorporated


Features Product Folder Order Now Technical Doc uments Tools & Software Support & Com munity DRA72 SPRS956F – MARCH 2016 REVISED JUNE 2018 DRA72x Infotainmen t Applications Processor Silicon Revisi on 2.0 1 Device Overview 1.1 Features 1 • Architecture Designed for Infota inment Applications • Video, Image, a nd Graphics Processing Support – Full -HD Video (1920 × 1080p, 60 fps) – M ultiple Video Input and Video Output 2D and 3D Graphics • Arm® Cortex® -A15 Microprocessor Subsystem • C66x Floating-Point VLIW DSP – Fully Objec t-Code Compatible With C67x and C64x+ Up to Thirty-two 16 × 16-Bit Fixed- Point Multiplies per Cycle • Up to 51 2KB of On-Chip L3 RAM • Level 3 (L3) and Level 4 (L4) Interconnects • DDR3 /DDR3L Memory Interface (EMIF) Module Supports up to DDR3-1333 (667 MHz) Up to 2GB Across Single Chip Select • Dual Arm® Cortex®-M4 Image Proces sing Units (IPU) • IVA-HD Subsystem Display Subsystem – Display Controller With DMA Engine and up to Three Pipelines – HDMI™ Encoder: HDMI 1.
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