Regulator Controller. LM2657 Datasheet

LM2657 Controller. Datasheet pdf. Equivalent


Part LM2657
Description Dual Synchronous Buck Regulator Controller
Feature LM2657 www.ti.com SNVS342B – JANUARY 2005 – REVISED MARCH 2013 LM2657 Dual Synchronous Buck Regul.
Manufacture etcTI
Datasheet
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LM2657 Dual Synchronous Buck Regulator Controller January 2 LM2657 Datasheet
LM2657 www.ti.com SNVS342B – JANUARY 2005 – REVISED MARCH LM2657 Datasheet
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LM2657
LM2657
www.ti.com
SNVS342B – JANUARY 2005 – REVISED MARCH 2013
LM2657 Dual Synchronous Buck Regulator Controller
Check for Samples: LM2657
FEATURES
1
2 Input Voltage Range from 4.5V to 28V
• Synchronous Dual-Channel Interleaved
Switching
• Forced-PWM or Pulse-Skip Modes
• Lossless Bottom-Side FET Current Sensing
• Adaptive Duty Cycle Clamp
• High Current N-Channel FET Drivers
• Low Shutdown Supply Current
• Reference Voltage Accurate to within ±1.5%
• Output Voltage Adjustable Down to 0.6V
• Power Good Flag and Chip Enable
• Under-Voltage Lockout
• Over-Voltage/Under-Voltage Protection
• Soft-Start
• Switching Frequency Adjustable 200kHz-
500kHz
• 28-Pin TSSOP Package
APPLICATIONS
• Low Output Voltage High-Efficiency Buck
Regulators
DESCRIPTION
The LM2657 is an adjustable 200kHz-500kHz dual
channel voltage-mode controlled high-speed
synchronous buck regulator controller ideally suited
for high current applications. The LM2657 requires
only N-channel FETs for both the upper and lower
positions of each stage. It features line feedforward to
improve the response to input transients. At very light
loads, the user can choose between the high-
efficiency Pulse-skip mode or the constant frequency
Forced-PWM mode. Lossless current limiting without
the use of external sense resistors is made possible
by sensing the voltage drop across the bottom FET.
A unique adaptive duty cycle clamping technique is
incorporated to significantly reduce peak currents
under abnormal load conditions. The two
independently programmable outputs switch 180° out
of phase (interleaved switching) reducing the input
capacitor and filter requirements. The input voltage
range is 4.5V to 28V while the output voltages are
adjustable down to 0.6V.
Standard supervisory and control features include
Soft-start, Power Good, output Under-voltage and
Over-voltage protection, Under-voltage Lockout, and
chip Enable.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2013, Texas Instruments Incorporated



LM2657
LM2657
SNVS342B – JANUARY 2005 – REVISED MARCH 2013
Typical Application (Channel 2 in parenthesis)
VIN
5V
FPWM VRON
R18
R17
POK
R20
VIN
BOOT1 (2)
FPWM
HDRV1 (2)
SW1 (2)
ILIM1 (2)
LDRV1 (2)
EN
PGOOD
PGND1 (2)
SENSE1 (2)
V5
COMP1 (2)
R1
VDD
FB1 (2)
FREQ
SS1 (2)
SGND
C29
R19
D2
(D1)
C30
(C28)
R8 (R7)
Q1
(Q4)
L1
(L2)
Q2
(Q5)
C32
(C1)
C25
(C22)
Vo1
(Vo2)
C26
(C23)
C31
C6 (C5)
R9 (R6)
C7 (C4)
C16
(C15)
R22
(R16)
C17
(C14)
R21
(R15)
R23
(R14)
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Connection Diagram
SENSE1
FB1
COMP1
SS1
VDD
FREQ
SGND
EN
PGOOD
FPWM
SS2
COMP2
FB2
SENSE2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 ILIM1
27 SW1
26 HDRV1
25 BOOT1
24 PGND1
23 LDRV1
22 VIN
21 V5
20 LDRV2
19 PGND2
18 BOOT2
17 HDRV2
16 SW2
15 ILIM2
Figure 1. 28-Pin TSSOP (Top View)
See PW Package
PIN DESCRIPTION
Pin 1, SENSE1:
Output voltage sense pin for Channel 1. It is tied directly to the output rail. The SENSE pin voltage is used by the IC,
together with the VIN voltage (Pin 22) to calculate the CCM (continuous conduction mode) duty cycle. This is used by the
IC to set the minimum duty cycle in the SKIP mode to 85% of the CCM value. It is also used to set the adaptive duty
cycle clamp (see Pin 3).
Pin 2, FB1:
Feedback pin for Channel 1. This is the inverting input of the channel’s error amplifier. The voltage on this pin under
regulation is nominally at 0.6V. A ‘Power Good window’ on this pin determines if the output voltage is within regulation
limits (±13%). If the voltage (on either channel) falls outside this window for more than 7µs, ‘Power Not Good’ is signaled
on the PGOOD pin (Pin 9). Additionally, if the FB voltage is above the upper limit, an over-voltage fault condition occurs
which turns on the low-side FET. The part will resume normal operation on the next high side cycle in which no fault is
detected. When single channel operation is desired (one channel is used, the other is disabled), the feedback pins of
both channels must be connected together, near the IC. All other pins specific to the unused channel should be left
floating (not connected to each other, either).
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Copyright © 2005–2013, Texas Instruments Incorporated





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