DC-DC Converter. TPS54560B-Q1 Datasheet

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TPS54560B-Q1
SLVSDP8 – FEBRUARY 2017
TPS54560B-Q1 4.5 V to 60 V Input, 5 A, Step Down DC-DC Converter with Eco-mode™
1 Features
1 High Efficiency at Light Loads with Pulse Skipping
Eco-mode™
• 92-mΩ High-Side MOSFET
• 146 μA Operating Quiescent Current and
2 μA Shutdown Current
• 100 kHz to 2.5 MHz Fixed Switching Frequency
• Synchronizes to External Clock
• Low Dropout at Light Loads with Integrated BOOT
Recharge FET
• Adjustable UVLO Voltage and Hysteresis
• 0.8 V 1% Internal Voltage Reference
• 8-Terminal HSOP with PowerPAD™ Package
• –40°C to 150°C TJ Operating Range
• Create a Custom Design using the
TPS54560B-Q1 with the WEBENCH® Power
Designer
2 Applications
• Industrial Automation and Motor Control
• Vehicle Accessories: GPS, Entertainment
• USB Dedicated Charging Ports and Battery
Chargers
• 12 V, 24 V and 48 V Industrial, Automotive and
Communications Power Systems
3 Description
The TPS54560B-Q1 is a 60 V, 5 A, step down
regulator with an integrated high side MOSFET. The
device survives load dump pulses up to 65V per ISO
7637. Current mode control provides simple external
compensation and flexible component selection. A
low ripple pulse skip mode reduces the no load
supply current to 146 μA. Shutdown supply current is
reduced to 2 μA when the enable pin is pulled low.
Undervoltage lockout is internally set at 4.3 V but can
be increased using the enable pin. The output voltage
start up ramp is internally controlled to provide a
controlled start up and eliminate overshoot.
A wide switching frequency range allows either
efficiency or external component size to be optimized.
Output current is limited cycle-by-cycle. Frequency
foldback and thermal shutdown protects internal and
external components during an overload condition.
The TPS54560B-Q1 is available in an 8-terminal
thermally enhanced HSOP PowerPAD™ package.
Device Information(1)
ORDER NUMBER
PACKAGE
BODY SIZE
TPS54560B-Q1
HSOP (8)
4.89 mm x 3.9 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
spacer
Simplified Schematic
VIN VIN BOOT
EN
COMP
SW
RT/CLK
FB
GND
VOUT
Efficiency vs Load Current
100
36 V to 12 V
95
90
85
12 V to 3.3 V
80
12 V to 5 V
75
70
65 VOUT = 12 V, fsw = 800 kHz
VOUT = 5 V and 3.3 V, fsw = 400 kHz
60
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
IO - Output Current (A)
C024
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.


TPS54560B-Q1 Datasheet
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Description Step Down DC-DC Converter
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TPS54560B-Q1
SLVSDP8 – FEBRUARY 2017
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Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information .................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Timing Requirements ................................................ 6
6.7 Typical Characteristics .............................................. 6
7 Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 11
7.3 Feature Description ................................................ 11
7.4 Device Functional Modes........................................ 22
8 Application and Implementation ........................ 23
8.1 Application Information............................................ 23
8.2 Typical Application .................................................. 23
8.3 Inverting Power ....................................................... 36
8.4 Split Rail Power Supply........................................... 36
9 Power Supply Recommendation ........................ 37
10 Layout................................................................... 38
10.1 Layout Guidelines ................................................. 38
10.2 Layout Examples................................................... 38
11 Device and Documentation Support ................. 39
11.1 Device Support...................................................... 39
11.2 Receiving Notification of Documentation Updates 39
11.3 Community Resources.......................................... 39
11.4 Trademarks ........................................................... 39
11.5 Electrostatic Discharge Caution ............................ 39
11.6 Glossary ................................................................ 39
12 Mechanical, Packaging, and Orderable
Information ........................................................... 39
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
February 2017
REVISION
*
INITIAL
Initial release
2 Submit Documentation Feedback
Product Folder Links: TPS54560B-Q1
Copyright © 2017, Texas Instruments Incorporated



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5 Pin Configuration and Functions
HSOP PACKAGE
(TOP VIEW)
BOOT
1
8
SW
TPS54560B-Q1
SLVSDP8 – FEBRUARY 2017
VIN 2
7
PowerPAD
EN 3
6
GND
COMP
RT/CLK
4
5 FB
PIN
NAME
NO.
BOOT
1
VIN 2
EN 3
RT/CLK
4
FB
COMP
GND
SW
Thermal Pad
5
6
7
8
Pin Functions
I/O DESCRIPTION
A bootstrap capacitor is required between BOOT and SW. If the voltage on this capacitor is below the
O minimum required to operate the high side MOSFET, the output is switched off until the capacitor is
refreshed.
I Input supply voltage with 4.5 V to 60 V operating range.
I
Enable terminal, with internal pull-up current source. Pull below 1.2 V to disable. Float to enable. Adjust the
input undervoltage lockout with two resistors. See the Enable and Adjusting Undervoltage Lockout section.
Resistor Timing and External Clock. An internal amplifier holds this terminal at a fixed voltage when using an
external resistor to ground to set the switching frequency. If the terminal is pulled above the PLL upper
I threshold, a mode change occurs and the terminal becomes a synchronization input. The internal amplifier is
disabled and the terminal is a high impedance clock input to the internal PLL. If clocking edges stop, the
internal amplifier is re-enabled and the operating mode returns to resistor frequency programming.
I Inverting input of the transconductance (gm) error amplifier.
O
Error amplifier output and input to the output switch current (PWM) comparator. Connect frequency
compensation components to this terminal.
– Ground
I The source of the internal high-side power MOSFET and switching node of the converter.
GND terminal must be electrically connected to the exposed pad on the printed circuit board for proper
operation.
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: TPS54560B-Q1
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