D-Type Flip-Flop. CD74HC174 Datasheet

CD74HC174 Flip-Flop. Datasheet pdf. Equivalent


etcTI CD74HC174
Data sheet acquired from Harris Semiconductor
SCHS159C
August 1997 - Revised October 2003
CD54HC174, CD74HC174,
CD54HCT174, CD74HCT174
High-Speed CMOS Logic
Hex D-Type Flip-Flop with Reset
[ /Title
(CD74
HC174
,
CD74
HCT17
4)
/Sub-
ject
(High
Speed
CMOS
Logic
Hex D-
Type
Flip-
Flop
Features
• Buffered Positive Edge Triggered Clock
• Asynchronous Common Reset
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il 1µA at VOL, VOH
Description
The ’HC174 and ’HCT174 are edge triggered flip-flops which
utilize silicon gate CMOS circuitry to implement D-type flip-
flops. They possess low power and speeds comparable to low
power Schottky TTL circuits. The devices contain six master-
slave flip-flops with a common clock and common reset.
Data on the D input having the specified setup and hold
times is transferred to the Q output on the low to high
transition of the CLOCK input. The MR input, when low, sets
all outputs to a low state.
Each output can drive ten low power Schottky TTL
equivalent loads. The ’HCT174 is functional as well as, pin
compatible to the ’LS174.
Ordering Information
PART NUMBER
TEMP. RANGE
(oC)
PACKAGE
CD54HC174F3A
-55 to 125
16 Ld CERDIP
CD54HCT174F3A
-55 to 125
16 Ld CERDIP
CD74HC174E
-55 to 125
16 Ld PDIP
CD74HC174M
-55 to 125
16 Ld SOIC
CD74HC174MT
-55 to 125
16 Ld SOIC
CD74HC174M96
-55 to 125
16 Ld SOIC
CD74HCT174E
-55 to 125
16 Ld PDIP
CD74HCT174M
-55 to 125
16 Ld SOIC
CD74HCT174MT
-55 to 125
16 Ld SOIC
CD74HCT174M96
-55 to 125
16 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel of
250.
Pinout
CD54HC174, CD54HCT174
(CERDIP)
CD74HC174, CD74HCT174
(PDIP, SOIC)
TOP VIEW
MR 1
Q0 2
D0 3
D1 4
Q1 5
D2 6
Q2 7
GND 8
16 VCC
15 Q5
14 D5
13 D4
12 Q4
11 D3
10 Q3
9 CP
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1


CD74HC174 Datasheet
Recommendation CD74HC174 Datasheet
Part CD74HC174
Description Hex D-Type Flip-Flop
Feature CD74HC174; Data sheet acquired from Harris Semiconductor SCHS159C August 1997 - Revised October 2003 CD54HC174.
Manufacture etcTI
Datasheet
Download CD74HC174 Datasheet




etcTI CD74HC174
CD54HC174, CD74HC174, CD54HCT174, CD74HCT174
Functional Diagram
CP
D0
CP
D Q0
R
D1 Q1
D2 Q2
D3 Q3
D4 Q4
D5
MR
Q5
TRUTH TABLE
INPUTS
OUTPUT
RESET (MR)
L
CLOCK CP
X
DATA Dn
X
Qn
L
H HH
H LL
H L X Q0
H = High Voltage Level, L = Low Voltage Level, X = Irrelevant, = Transition from Low to
High Level, Q0 = Level Before the Indicated Steady-State Input Conditions Were Established
Logic Diagram
3 (4, 6, 11, 13, 14) D
Dn
CL
p
n
CL
1
MR
9
CP
R
CL
p
n
CL
CL
p
n
CL
CL
CP
ONE OF SIX F/F
CL
p
n
CL CL
TO OTHER FIVE F/F
TO OTHER FIVE F/F
Q 2 (5, 7, 10, 12, 15)
Qn
8 16
VCC
2



etcTI CD74HC174
CD54HC174, CD74HC174, CD54HCT174, CD74HCT174
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA
Thermal Information
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . .
67
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . .
73
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
PARAMETER
HC TYPES
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
CMOS Loads
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
SYMBOL
TEST
CONDITIONS
25oC
-40oC TO +85oC
VI (V) IO (mA) VCC (V) MIN TYP MAX MIN
MAX
-55oC TO 125oC
MIN MAX UNITS
VIH -
-
VIL - -
VOH
VIH or
VIL
-0.02
-0.02
-0.02
-4
-5.2
2 1.5 - - 1.5 - 1.5 -
4.5 3.15 -
- 3.15
- 3.15
-
6 4.2 - - 4.2 - 4.2 -
2 - - 0.5 - 0.5 - 0.5
4.5
-
- 1.35
-
1.35
-
1.35
6 - - 1.8 - 1.8 - 1.8
2 1.9 - - 1.9 - 1.9 -
4.5 4.4 - - 4.4
- 4.4
-
6 5.9 - - 5.9 - 5.9 -
4.5 3.98 -
- 3.84
-
3.7
-
6 5.48 -
- 5.34
-
5.2
-
V
V
V
V
V
V
V
V
V
V
V
VOL VIH or 0.02
2
- - 0.1 -
0.1
-
VIL 0.02 4.5 - - 0.1 - 0.1 -
0.02 6
- - 0.1 -
0.1
-
4
4.5
-
- 0.26
-
0.33
-
5.2
6
-
- 0.26
-
0.33
-
0.1 V
0.1 V
0.1 V
0.4 V
0.4 V
II
VCC or
-
GND
6
-
- ±0.1
-
±1
-
±1 µA
ICC VCC or 0 6 - - 8 - 80 - 160 µA
GND
3







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