Up/Down Counters. CD74HC193 Datasheet

CD74HC193 Counters. Datasheet pdf. Equivalent


etcTI CD74HC193
CD54/74HC192,
CD54/74HC193, CD54/74HCT193
Data sheet acquired from Harris Semiconductor
SCHS163F
High-Speed CMOS Logic
September 1997 - Revised October 2003 Presettable Synchronous 4-Bit Up/Down Counters
[ /Title
(CD74
HC192
,
CD74
HC193
,
CD74
HCT19
3)
/Sub-
ject
(High
Speed
CMOS
Logic
Preset-
Features
• Synchronous Counting and Asynchronous
Loading
• Two Outputs for N-Bit Cascading
• Look-Ahead Carry for High-Speed Counting
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il 1µA at VOL, VOH
Description
The ’HC192, ’HC193 and ’HCT193 are asynchronously
presettable BCD Decade and Binary Up/Down synchronous
counters, respectively.
Presetting the counter to the number on the preset data inputs
(P0-P3) is accomplished by a LOW asynchronous parallel
load input (PL). The counter is incremented on the low-to-high
transition of the Clock-Up input (and a high level on the Clock-
Down input) and decremented on the low to high transition of
the Clock-Down input (and a high level on the Clock-up input).
A high level on the MR input overrides any other input to clear
the counter to its zero state. The Terminal Count up (carry)
goes low half a clock period before the zero count is reached
and returns to a high level at the zero count. The Terminal
Count Down (borrow) in the count down mode likewise goes
low half a clock period before the maximum count (9 in the
192 and 15 in the 193) and returns to high at the maximum
count. Cascading is effected by connecting the carry and
borrow outputs of a less significant counter to the Clock-Up
and Clock-Down inputs, respectively, of the next most
significant counter.
If a decade counter is preset to an illegal state or assumes an
illegal state when power is applied, it will return to the normal
sequence in one count as shown in state diagram.
Ordering Information
PART NUMBER
CD54HC192F3A
CD54HC193F3A
CD54HCT193F3A
CD74HC192E
TEMP. RANGE
(oC)
PACKAGE
-55 to 125 16 Ld CERDIP
-55 to 125 16 Ld CERDIP
-55 to 125 16 Ld CERDIP
-55 to 125 16 Ld PDIP
CD74HC192NSR
-55 to 125 16 Ld SOP
Pinout
CD54HC192, CD54HC193, CD54HCT193 (CERDIP)
CD74HC192 (PDIP, SOP, TSSOP)
CD74HC193 (PDIP, SOIC)
CD74HCT193 (PDIP)
TOP VIEW
P1 1
Q1 2
Q0 3
CPD 4
CPU 5
Q2 6
Q3 7
GND 8
16 VCC
15 P0
14 MR
13 TCD
12 TCU
11 PL
10 P2
9 P3
CD74HC192PW
-55 to 125 16 Ld TSSOP
CD74HC192PWR
-55 to 125 16 Ld TSSOP
CD74HC192PWT
-55 to 125 16 Ld TSSOP
CD74HC193E
-55 to 125 16 Ld PDIP
CD74HC193M
-55 to 125 16 Ld SOIC
CD74HC193MT
-55 to 125 16 Ld SOIC
CD74HC193M96
-55 to 125 16 Ld SOIC
CD74HCT193E
-55 to 125 16 Ld PDIP
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1


CD74HC193 Datasheet
Recommendation CD74HC193 Datasheet
Part CD74HC193
Description Presettable Synchronous 4-Bit Up/Down Counters
Feature CD74HC193; CD54/74HC192, CD54/74HC193, CD54/74HCT193 Data sheet acquired from Harris Semiconductor SCHS163F H.
Manufacture etcTI
Datasheet
Download CD74HC193 Datasheet




etcTI CD74HC193
CD54/74HC192, CD54/74HC193, CD54/74HCT193
Functional Diagram
BCD/BINARY
PRESET
P0 P1 P2 P3
ASYN.
PARALLEL
LOAD
ENABLE
15
11
PL
MASTER 14
RESET
1 10
9
5
CLOCK UP
4
CLOCK DOWN
3
Q0
2
Q1 BCD (192)
6
Q2
BINARY (193)
OUTPUTS
7
Q3
12 TERMINAL
COUNT UP
13
TERMINAL
COUNT DOWN
TRUTH TABLE
CLOCK UP
CLOCK
DOWN
RESET
PARALLEL
LOAD
FUNCTION
H L H Count Up
H L H Count Down
X X H X Reset
X X L L Load Preset Inputs
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, = Transition from Low to
High Level
2



etcTI CD74HC193
CD54/74HC192, CD54/74HC193, CD54/74HCT193
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Package Thermal Impedance, θJA (see Note 1):
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67oC/W
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73oC/W
NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64oC/W
PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 108oC/W
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
PARAMETER
HC TYPES
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
CMOS Loads
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
SYMBOL
TEST
CONDITIONS
VI (V) IO (mA) VCC (V)
MIN
25oC
TYP MAX
VIH -
-
VIL - -
VOH
VOL
II
ICC
VIH or
VIL
-0.02
-0.02
-0.02
-4
-5.2
VIH or
VIL
0.02
0.02
0.02
4
5.2
VCC or
GND
VCC or
GND
-
0
2 1.5 - -
4.5 3.15 -
-
6 4.2 - -
2 - - 0.5
4.5 - - 1.35
6 - - 1.8
2 1.9 - -
4.5 4.4 -
-
6 5.9 - -
4.5 3.98 -
-
6 5.48 -
-
2 - - 0.1
4.5 - - 0.1
6 - - 0.1
4.5 - - 0.26
6 - - 0.26
6 - - ±0.1
6 - -8
-40oC TO 85oC
MIN MAX
1.5 -
3.15 -
4.2 -
- 0.5
- 1.35
- 1.8
1.9 -
4.4 -
5.9 -
3.84 -
5.34 -
- 0.1
- 0.1
- 0.1
- 0.33
- 0.33
- ±1
- 80
-55oC TO 125oC
MIN MAX UNITS
1.5 -
3.15 -
4.2 -
- 0.5
- 1.35
- 1.8
1.9 -
4.4 -
5.9 -
3.7 -
5.2 -
V
V
V
V
V
V
V
V
V
V
V
- 0.1 V
- 0.1 V
- 0.1 V
- 0.4 V
- 0.4 V
- ±1 µA
- 160 µA
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