SN74LV08A-EP Positive-AND Gates Datasheet

SN74LV08A-EP Datasheet, PDF, Equivalent


Part Number

SN74LV08A-EP

Description

Quadruple 2-Input Positive-AND Gates

Manufacture

etcTI

Total Page 10 Pages
Datasheet
Download SN74LV08A-EP Datasheet


SN74LV08A-EP
www.ti.com
FEATURES
Controlled Baseline
– One Assembly/Test Site, One Fabrication
Site
Extended Temperature Performance of
–55°C to 125°C
Enhanced Diminishing Manufacturing
Sources (DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree (1)
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 3.3 V, TA = 25°C
Supports Mixed-Mode Voltage Operation on
All Ports
Ioff Supports Partial-Power-Down Mode
Operation
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
SN74LV08A-EP
QUADRUPLE 2-INPUT POSITIVE-AND GATE
SCLS481B – MAY 2003 – REVISED JANUARY 2006
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
PW PACKAGE
(TOP VIEW)
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
14 VCC
13 4B
12 4A
11 4Y
10 3B
9 3A
8 3Y
DESCRIPTION/ORDERING INFORMATION
This quadruple 2-input positive-AND gate is designed for 2-V to 5.5-V VCC operation.
The SN74LV08A-EP performs the Boolean function Y = A S B or Y = A + B in positive logic.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
–40°C to 105°C
–55°C to 125°C
PACKAGE (1)
TSSOP – PW
Tape and reel
TSSOP – PW
Tape and reel
ORDERABLE PART NUMBER
SN74LV08ATPWREP
SN74LV08AMPWREP
TOP-SIDE MARKING
LV08AEP
LV08AEP
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
FUNCTION TABLE
(EACH GATE)
INPUTS
AB
HH
LX
XL
OUTPUT
Y
H
L
L
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2006, Texas Instruments Incorporated

SN74LV08A-EP
SN74LV08A-EP
QUADRUPLE 2-INPUT POSITIVE-AND GATE
SCLS481B – MAY 2003 – REVISED JANUARY 2006
LOGIC DIAGRAM, EACH GATE (POSITIVE LOGIC)
A
Y
B
www.ti.com
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
VCC Supply voltage range
VI Input voltage range(2)
VO Voltage range applied to any output in the high-impedance or power-off state(2)
VO Output voltage range(2)(3)
IIK Input clamp current
VI < 0
IOK Output clamp current
VO < 0
IO Continuous output current
VO = 0 to VCC
Continuous current through VCC or GND
θJA Package thermal impedance(4)
Tstg Storage temperature range
MIN
–0.5
–0.5
–0.5
–0.5
–65
MAX
7
7
7
VCC + 0.5
–20
–50
±25
±50
113
150
UNIT
V
V
V
V
mA
mA
mA
mA
°C/W
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) This value is limited to 5.5 V maximum.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
2


Features www.ti.com FEATURES • Controlled Basel ine – One Assembly/Test Site, One Fab rication Site • Extended Temperature Performance of –55°C to 125°C • E nhanced Diminishing Manufacturing Sourc es (DMS) Support • Enhanced Product-C hange Notification • Qualification Pe digree (1) • Typical VOLP (Output Gro und Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C • Typical VOHV (Output VOH Und ershoot) >2.3 V at VCC = 3.3 V, TA = 25 °C • Supports Mixed-Mode Voltage Ope ration on All Ports • Ioff Supports P artial-Power-Down Mode Operation (1) Co mponent qualification in accordance wit h JEDEC and industry standards to ensur e reliable operation over an extended t emperature range. This includes, but is not limited to, Highly Accelerated Str ess Test (HAST) or biased 85/85, temper ature cycle, autoclave or unbiased HAST , electromigration, bond intermetallic life, and mold compound life. Such qual ification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
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