SN74LV11A-Q1 POSITIVE-AND GATES Datasheet

SN74LV11A-Q1 Datasheet, PDF, Equivalent


Part Number

SN74LV11A-Q1

Description

TRIPLE 3-INPUT POSITIVE-AND GATES

Manufacture

etcTI

Total Page 12 Pages
Datasheet
Download SN74LV11A-Q1 Datasheet


SN74LV11A-Q1
SN74LV11A-Q1
TRIPLE 3-INPUT POSITIVE-AND GATE
D Qualified for Automotive Applications
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D 2-V to 5.5-V VCC Operation
D Typical VOLP (Output Ground Bounce)
<0.8 V at VCC= 3.3 V, TA = 25°C
D Typical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 3.3 V, TA = 25°C
D Support Mixed-Mode Voltage Operation on
All Ports
D Ioff Supports Partial-Power-Down Mode
Operation
SCES468D − JULY 2003 − REVISED JANUARY 2008
PW PACKAGE
(TOP VIEW)
1A
1B
2A
2B
2C
2Y
GND
1
2
3
4
5
6
7
14 VCC
13 1C
12 1Y
11 3C
10 3B
9 3A
8 3Y
description/ordering information
This triple 3-input positive-AND gate is designed for 2-V to 5.5-V VCC operation.
The SN74LV11A performs the Boolean function Y + A B C or Y + A ) B ) C in positive logic.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
−40°C to 105°C TSSOP − PW Tape and reel SN74LV11ATPWRQ1 LV11AT
For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
FUNCTION TABLE
(each gate)
INPUTS
ABC
OUTPUT
Y
HHH
H
LXX
L
XLX
L
XXL
L
logic diagram, each gate (positive logic)
A
B
C
Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2008, Texas Instruments Incorporated
1

SN74LV11A-Q1
SN74LV11A-Q1
TRIPLE 3-INPUT POSITIVE-AND GATE
SCES468D − JULY 2003 − REVISED JANUARY 2008
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Output voltage range applied in high or low state, VO (see Notes 1 and 2) . . . . . . . . . . −0.5 V to VCC + 0.5 V
Voltage range applied to any output in the power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 4)
MIN MAX UNIT
VCC Supply voltage
2 5.5 V
VCC = 2 V
1.5
VIH High-level input voltage
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC × 0.7
VCC × 0.7
V
VCC = 4.5 V to 5.5 V
VCC × 0.7
VCC = 2 V
0.5
VIL Low-level input voltage
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC × 0.3
VCC × 0.3
V
VCC = 4.5 V to 5.5 V
VCC × 0.3
VI Input voltage
0 5.5 V
VO Output voltage
0 VCC V
VCC = 2 V
−50 µA
IOH High-level output current
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
−2
−6 mA
VCC = 4.5 V to 5.5 V
−12
VCC = 2 V
50 µA
IOL Low-level output current
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
2
6 mA
VCC = 4.5 V to 5.5 V
12
VCC = 2.3 V to 2.7 V
200
t/v Input transition rise or fall rate
VCC = 3 V to 3.6 V
100 ns/V
VCC = 4.5 V to 5.5 V
20
TA Operating free-air temperature
−40 105 °C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265


Features SN74LV11A-Q1 TRIPLE 3-INPUT POSITIVE-AND GATE D Qualified for Automotive Appli cations D ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) D 2-V to 5.5-V VCC Operation D T ypical VOLP (Output Ground Bounce) <0.8 V at VCC= 3.3 V, TA = 25°C D Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25°C D Support Mixed -Mode Voltage Operation on All Ports D Ioff Supports Partial-Power-Down Mode O peration SCES468D − JULY 2003 − RE VISED JANUARY 2008 PW PACKAGE (TOP VIEW ) 1A 1B 2A 2B 2C 2Y GND 1 2 3 4 5 6 7 14 VCC 13 1C 12 1Y 11 3C 10 3B 9 3A 8 3Y description/ordering information T his triple 3-input positive-AND gate is designed for 2-V to 5.5-V VCC operatio n. The SN74LV11A performs the Boolean f unction Y + A • B • C or Y + A ) B ) C in positive logic. This device is f ully specified for partial-power-down a pplications using Ioff. The Ioff circui try disables the outputs, preventing damaging current backflow through th.
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