SN74LV125A-Q1 Buffer Gates Datasheet

SN74LV125A-Q1 Datasheet, PDF, Equivalent


Part Number

SN74LV125A-Q1

Description

Quadruple Bus Buffer Gates

Manufacture

etcTI

Total Page 14 Pages
Datasheet
Download SN74LV125A-Q1 Datasheet


SN74LV125A-Q1
SN74LV125A-Q1
www.ti.com
SCES814 – SEPTEMBER 2010
QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS
Check for Samples: SN74LV125A-Q1
FEATURES
1
• Qualified for Automotive Applications
• 2-V to 5.5-V VCC Operation
• Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
• Typical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 3.3 V, TA = 25°C
• Support Mixed-Mode Voltage Operation on All
Ports
• Ioff Supports Partial-Power-Down Mode
Operation
RGY PACKAGE
(TOP VIEW)
1A
1Y
2OE
2A
2Y
2
3
4
5
6
1
7
14
13 4OE
12 4A
11 4Y
10 3OE
9 3A
8
DESCRIPTION
The SN74LV125A-Q1 quadruple bus buffer gate is designed for 2-V to 5.5-V VCC operation.
This device features independent line drivers with 3-state outputs. Each output is disabled when the associated
output-enable (OE) input is high.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the devices when they are powered down.
TA
–40°C to 125°C
QFN – RGY
ORDERING INFORMATION
PACKAGE (1)
ORDERABLE PART NUMBER
Reel of 3000
SN74LV125AQRGYRQ1
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
TOP-SIDE MARKING
LV125Q
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated

SN74LV125A-Q1
SN74LV125A-Q1
SCES814 – SEPTEMBER 2010
1
1OE
2
1A
4
2OE
5
2A
FUNCTION TABLE
(EACH BUFFER)
INPUTS
OE A
OUTPUT
Y
L HH
LLL
HXZ
LOGIC DIAGRAM (POSITIVE LOGIC)
10
3OE
3
1Y
9
3A
13
4OE
6
2Y
12
4A
www.ti.com
8
3Y
11
4Y
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage range
VI Input voltage range(2)
VO Voltage range applied to any output in the high-impedance or power-off state(2)
VO Output voltage range(2) (3)
IIK Input clamp current
VI < 0
IOK Output clamp current
VO < 0
IO Continuous output current
VO = 0 to VCC
Continuous current through VCC or GND
qJA Package thermal impedance(4)
RGY package
Tstg Storage temperature range
–0.5
–0.5
–0.5
–0.5
–65
7
7
7
VCC + 0.5
–20
–50
±35
±70
47
150
V
V
V
V
mA
mA
mA
mA
°C/W
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) This value is limited to 5.5 V maximum.
(4) The package thermal impedance is calculated in accordance with JESD 51-5.
2 Submit Documentation Feedback
Product Folder Link(s): SN74LV125A-Q1
Copyright © 2010, Texas Instruments Incorporated


Features SN74LV125A-Q1 www.ti.com SCES814 – S EPTEMBER 2010 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS Check for Samples : SN74LV125A-Q1 FEATURES 1 • Qualifi ed for Automotive Applications • 2-V to 5.5-V VCC Operation • Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C • Typical VOHV (Ou tput VOH Undershoot) >2.3 V at VCC = 3. 3 V, TA = 25°C • Support Mixed-Mode Voltage Operation on All Ports • Ioff Supports Partial-Power-Down Mode Opera tion RGY PACKAGE (TOP VIEW) 1OE VCC 1A 1Y 2OE 2A 2Y 2 3 4 5 6 1 7 14 13 4OE 12 4A 11 4Y 10 3OE 9 3A 8 GND 3Y DESCRIPTION The SN74LV125A-Q1 quadruple bus buffer gate is designed for 2-V to 5.5-V VCC operation. This device featu res independent line drivers with 3-sta te outputs. Each output is disabled whe n the associated output-enable (OE) inp ut is high. To ensure the high-impedanc e state during power up or power down, OE should be tied to VCC through a pull up resistor; the minimum value of the resistor is determined by the current-sin.
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