CD74HC4040 Binary Counter Datasheet

CD74HC4040 Datasheet, PDF, Equivalent


Part Number

CD74HC4040

Description

12-Stage Binary Counter

Manufacture

etcTI

Total Page 17 Pages
Datasheet
Download CD74HC4040 Datasheet


CD74HC4040
Data sheet acquired from Harris Semiconductor
SCHS203D
February 1998 - Revised October 2003
CD54HC4040, CD74HC4040,
CD54HCT4040, CD74HCT4040
High-Speed CMOS Logic
12-Stage Binary Counter
[ /Title
(CD74H
C4040,
CD74HC
T4040)
/Subject
(High
Speed
CMOS
Logic
12-Stage
Binary
Features
Description
• Fully Static Operation
• Buffered Inputs
• Common Reset
• Negative Edge Pulsing
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il 1µA at VOL, VOH
The ’HC4040 and ’HCT4040 are 14-stage ripple-carry
binary counters. All counter stages are master-slave flip-
flops. The state of the stage advances one count on the
negative clock transition of each input pulse; a high voltage
level on the MR line resets all counters to their zero state. All
inputs and outputs are buffered.
Ordering Information
PART NUMBER
CD54HC4040F3A
CD54HCT4040F3A
CD74HC4040E
CD74HC4040M
CD74HC4040MT
CD74HC4040M96
CD74HC4040NSR
CD74HCT4040E
CD74HCT4040M
CD74HCT4040MT
TEMP. RANGE
(oC)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
16 Ld CERDIP
16 Ld CERDIP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld SOP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
CD74HCT4040M96
-55 to 125
16 Ld SOIC
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
Pinout
CD54HC4040, CD54HCT4040
(CERDIP)
CD74HC4040
(PDIP, SOIC, SOP)
CD74HCT4040
(PDIP, SOIC)
TOP VIEW
Q12 1
Q6 2
Q5 3
Q7 4
Q4 5
Q3 6
Q2 7
GND 8
16 VCC
15 Q11
14 Q10
13 Q8
12 Q9
11 MR
10 CP
9 Q1
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1

CD74HC4040
CD54HC4040, CD74HC4040, CD54HCT4040, CD74HCT4040
Functional Diagram
VCC
16
10
INPUT
PULSES
11
MASTER
RESET
12-STAGE
RIPPLE
COUNTER
8
GND
9
7 Q1
6 Q2
Q3
5
Q4
3
2 Q5
4 Q6
13 Q7
Q8
12
Q9
14
Q10
15
Q11
1
Q12
BUFFERED
OUTPUTS
TRUTH TABLE
CP COUNT
MR
OUTPUT STATE
L
No Change
L
Advance to Next State
XH
All Outputs Are Low
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care,
= Transition from Low to High Level, = Transition from High to Low.
2


Features Data sheet acquired from Harris Semicond uctor SCHS203D February 1998 - Revised October 2003 CD54HC4040, CD74HC4040, C D54HCT4040, CD74HCT4040 High-Speed CMOS Logic 12-Stage Binary Counter [ /Titl e (CD74H C4040, CD74HC T4040) /Subject (High Speed CMOS Logic 12-Stage Binary Features Description • Fully Stati c Operation • Buffered Inputs • Com mon Reset • Negative Edge Pulsing • Fanout (Over Temperature Range) - Stan dard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loa ds • Wide Operating Temperature Range . . . -55oC to 125oC • Balanced Prop agation Delay and Transition Times • Significant Power Reduction Compared t o LSTTL Logic ICs • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH The ’HC4040 and ’HCT4040 are 14-stage rip.
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