CD54HC40103 Down Counters Datasheet

CD54HC40103 Datasheet, PDF, Equivalent


Part Number

CD54HC40103

Description

8-Stage Synchronous Down Counters

Manufacture

etcTI

Total Page 18 Pages
Datasheet
Download CD54HC40103 Datasheet


CD54HC40103
Data sheet acquired from Harris Semiconductor
SCHS221D
November 1997 - Revised October 2003
CD54HC40103, CD74HC40103,
CD74HCT40103
High-Speed CMOS Logic
8-Stage Synchronous Down Counters
[ /Title
(CD74H
C40103,
CD74H
CT4010
3)
/Sub-
ject
(High
Speed
CMOS
Logic 8-
Features
Description
• Synchronous or Asynchronous Preset
• Cascadable in Synchronous or Ripple Mode
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il 1µA at VOL, VOH
Ordering Information
PART NUMBER
TEMP. RANGE
(oC)
PACKAGE
CD54HC40103F3A
-55 to 125
16 Ld CERDIP
CD74HC40103E
-55 to 125
16 Ld PDIP
CD74HC40103M
-55 to 125
16 Ld SOIC
CD74HC40103MT
-55 to 125
16 Ld SOIC
CD74HC40103M96
-55 to 125
16 Ld SOIC
CD74HCT40103E
-55 to 125
16 Ld PDIP
CD74HCT40103M
-55 to 125
16 Ld SOIC
CD74HCT40103MT
-55 to 125
16 Ld SOIC
CD74HCT40103M96
-55 to 125
16 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel
of 250.
The ’HC40103 and CD74HCT40103 are manufactured with
high speed silicon gate technology and consist of an 8-stage
synchronous down counter with a single output which is
active when the internal count is zero. The 40103 contains a
single 8-bit binary counter. Each has control inputs for
enabling or disabling the clock, for clearing the counter to its
maximum count, and for presetting the counter either
synchronously or asynchronously. All control inputs and the
TC output are active-low logic.
In normal operation, the counter is decremented by one
count on each positive transition of the CLOCK (CP).
Counting is inhibited when the TE input is high. The TC
output goes low when the count reaches zero if the TE input
is low, and remains low for one full clock period.
When the PE input is low, data at the P0-P7 inputs are
clocked into the counter on the next positive clock transition
regardless of the state of the TE input. When the PL input is
low, data at the P0-P7 inputs are asynchronously forced into
the counter regardless of the state of the PE, TE, or CLOCK
inputs. Input P0-P7 represent a single 8-bit binary word for
the 40103. When the MR input is low, the counter is
asynchronously cleared to its maximum count of 25510,
regardless of the state of any other input. The precedence
relationship between control inputs is indicated in the truth
table.
If all control inputs except TE are high at the time of zero
count, the counters will jump to the maximum count, giving a
counting sequence of 10016 or 25610 clock pulses long.
The 40103 may be cascaded using the TE input and the TC
output, in either a synchronous or ripple mode. These
circuits possess the low power consumption usually
associated with CMOS circuitry, yet have speeds
comparable to low power Schottky TTL circuits and can drive
up to 10 LSTTL loads.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1

CD54HC40103
Pinout
CD54HC40103, CD74HC40103, CD74HCT40103
CD54HC40103
(CERDIP)
CD74HC40103, CD74HCT40103
(PDIP, SOIC)
TOP VIEW
CP 1
MR 2
TE 3
P0 4
P1 5
P2 6
P3 7
GND 8
16 VCC
15 PE (SYNC)
14 TC
13 P7
12 P6
11 P5
10 P4
9 PL (ASYNC)
Functional Diagram
14
P7
13
12 P6
11 P5
10 P4
7 P3
6 P2
5 P1
P0
4
15 9 3 1 2
16 8
TRUTH TABLE
CONTROL INPUTS
MR PL PE TE PRESET MODE
ACTION
1111
Synchronous
Inhibit Counter
1110
Count Down
110X
Preset On Next Positive Clock Transition
1 0 X X Asynchronously Preset Asychronously
0XXX
Clear to Maximum Count
1 = High Level.
0 = Low Level.
X = Don’t Care.
Clock connected to clock input.
Synchronous Operation: changes occur on negative-to-positive clock transitions.
Load Inputs: MSB = P7, LSB = P0.
2


Features Data sheet acquired from Harris Semicond uctor SCHS221D November 1997 - Revised October 2003 CD54HC40103, CD74HC40103, CD74HCT40103 High-Speed CMOS Logic 8-S tage Synchronous Down Counters [ /Titl e (CD74H C40103, CD74H CT4010 3) /Subje ct (High Speed CMOS Logic 8- Features Description • Synchronous or Asynch ronous Preset • Cascadable in Synchro nous or Ripple Mode • Fanout (Over Te mperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loa ds - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Oper ating Temperature Range . . . -55oC to 125oC • Balanced Propagation Delay an d Transition Times • Significant Pow er Reduction Compared to LSTTL Logic IC s • HC Types - 2V to 6V Operation - H igh Noise Immunity: NIL = 30%, NIH = 30 % of VCC at VCC = 5V • HCT Types - 4. 5V to 5.5V Operation - Direct LSTTL Inp ut Logic Compatibility, VIL= 0.8V (Max) , VIH = 2V (Min) - CMOS Input Compatibi lity, Il ≤ 1µA at VOL, VOH Ordering Information PART NUMBER TEMP. RANGE (oC) P.
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