CD74HC40103-Q1 DOWN COUNTER Datasheet

CD74HC40103-Q1 Datasheet, PDF, Equivalent


Part Number

CD74HC40103-Q1

Description

8-STAGE SYNCHRONOUS DOWN COUNTER

Manufacture

etcTI

Total Page 13 Pages
Datasheet
Download CD74HC40103-Q1 Datasheet


CD74HC40103-Q1
D Qualified for Automotive Applications
D Synchronous or Asynchronous Preset
D Cascadable in Synchronous or Ripple
Mode
D Fanout (Over Temperature Range)
− Standard Outputs . . . 10 LSTTL Loads
− Bus Driver Outputs . . . 15 LSTTL Loads
D Balanced Propagation Delay and Transition
Times
D Significant Power Reduction Compared to
LSTTL Logic ICs
description/ordering information
CD74HC40103-Q1
HIGH-SPEED CMOS LOGIC
8-STAGE SYNCHRONOUS DOWN COUNTER
SCLS547A − OCTOBER 2003 − REVISED APRIL 2008
D VCC Voltage = 2 V to 6 V
D High Noise Immunity NIL or NIH = 30% of
VCC, VCC = 5 V
M PACKAGE
(TOP VIEW)
CP
MR
TE
P0
P1
P2
P3
GND
1
2
3
4
5
6
7
8
16 VCC
15 PE (SYNC)
14 TC
13 P7
12 P6
11 P5
10 P4
9 PL (ASYNC)
The CD74HC40103 is manufactured with high-speed silicon-gate technology and consists of an 8-stage
synchronous down counter with a single output, which is active when the internal count is zero. The device
contains a single 8-bit binary counter. Each device has control inputs for enabling or disabling the clock, for
clearing the counter to its maximum count, and for presetting the counter either synchronously or
asynchronously. All control inputs and the terminal count (TC) output are active-low logic.
In normal operation, the counter is decremented by one count on each positive transition of the clock (CP)
output. Counting is inhibited when the terminal enable (TE) input is high. TC goes low when the count reaches
zero, if TE is low, and remains low for one full clock period.
When the synchronous preset enable (PE) input is low, data at the P0−P7 inputs are clocked into the counter on
the next positive clock transition, regardless of the state of TE. When the asynchronous preset enable (PL) input
is low, data at the P0−P7 inputs asynchronously are forced into the counter, regardless of the state of the PE, TE,
or CP inputs. Inputs P0−P7 represent a single 8-bit binary word for the CD74HC40103. When the master reset
(MR) input is low, the counter asynchronously is cleared to its maximum count of 25510, regardless of the state of
any other input. The precedence relationship between control inputs is indicated in the truth table.
If all control inputs except TE are high at the time of zero count, the counters jump to the maximum count, giving a
counting sequence of 10016 or 25610 clock pulses long.
ORDERING INFORMATION{
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
−40°C to 125°C SOIC − M
Tape and reel CD74HC40103QM96Q1 HC40103Q
For the most current package and ordering information, see the Package Option Addendum at the
end of this document, or see the TI web site at http://www.ti.com.
Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2008, Texas Instruments Incorporated
1

CD74HC40103-Q1
CD74HC40103-Q1
HIGH-SPEED CMOS LOGIC
8-STAGE SYNCHRONOUS DOWN COUNTER
SCLS547A − OCTOBER 2003 − REVISED APRIL 2008
description/ordering information (continued)
The CD74HC40103 may be cascaded using the TE input and the TC output, in either synchronous or ripple
mode. These circuits have the low power consumption usually associated with CMOS circuitry, yet have speeds
comparable to low-power Schottky TTL circuits and can drive up to ten LSTTL loads.
FUNCTION TABLE
CONTROL INPUTS
MR PL PE TE
PRESET MODE
ACTION
HHHH
Inhibit counter
HHH L
HHL X
Synchronous
Count down
Preset on next positive clock transition
HLXX
LXXX
Asynchronous
Preset asynchronously
Clear to maximum count
NOTE: H = high voltage level, L = low voltage level, X = don’t care
Clock connected to clock input
Synchronous operation: changes occur on negative-to-positive clock transitions.
Load inputs: MSB = P7, LSB = P0
logic diagram (positive logic)
14
13 P7
12 P6
11 P5
10 P4
7 P3
6 P2
5 P1
P0
4
15 9 3 1 2
16 8
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265


Features D Qualified for Automotive Applications D Synchronous or Asynchronous Preset D Cascadable in Synchronous or Ripple Mod e D Fanout (Over Temperature Range) − Standard Outputs . . . 10 LSTTL Loads − Bus Driver Outputs . . . 15 LSTTL L oads D Balanced Propagation Delay and T ransition Times D Significant Power Red uction Compared to LSTTL Logic ICs desc ription/ordering information CD74HC401 03-Q1 HIGH-SPEED CMOS LOGIC 8-STAGE SYN CHRONOUS DOWN COUNTER SCLS547A − OCTO BER 2003 − REVISED APRIL 2008 D VCC V oltage = 2 V to 6 V D High Noise Immuni ty NIL or NIH = 30% of VCC, VCC = 5 V M PACKAGE (TOP VIEW) CP MR TE P0 P1 P2 P3 GND 1 2 3 4 5 6 7 8 16 VCC 15 PE ( SYNC) 14 TC 13 P7 12 P6 11 P5 10 P4 9 P L (ASYNC) The CD74HC40103 is manufactu red with high-speed silicon-gate techno logy and consists of an 8-stage synchro nous down counter with a single output, which is active when the internal coun t is zero. The device contains a single 8-bit binary counter. Each device has control inputs for enabling or d.
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