CD54HCT4017 DECADE COUNTER/DIVIDER Datasheet

CD54HCT4017 Datasheet, PDF, Equivalent


Part Number

CD54HCT4017

Description

DECADE COUNTER/DIVIDER

Manufacture

etcTI

Total Page 11 Pages
Datasheet
Download CD54HCT4017 Datasheet


CD54HCT4017
D 4.5-V to 5.5-V Operation
D Fully Static Operation
D Buffered Inputs
D Common Reset
D Positive-Edge Clocking
D Balanced Propagation Delay and Transition
Times
D Direct LSTTL Input Logic Compatibility
– VIL = 0.8 V Maximum; VIH = 2 V Minimum
D CMOS Input Compatibility
– II 1 µA at VOL, VOH
D Packaged in Ceramic (F) DIP Packages and
Also Available in Chip Form (H)
CD54HCT4017
DECADE COUNTER/DIVIDER
WITH TEN DECODED OUTPUTS
SGDS012 – MAY 1999
F PACKAGE
(TOP VIEW)
5
1
0
2
6
7
3
GND
1
2
3
4
5
6
7
8
16 VCC
15 MR
14 CP
13 CE
12 TC
11 9
10 4
98
description
The CD54HCT4017 is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs.
Each decoded output normally is low and sequentially goes high on the low-to-high transition of the clock (CP)
input. Each output stays high for one clock period of the ten-clock-period cycle. The terminal count (TC) output
transitions low to high after output ten (9) goes low, and can be used in conjunction with the clock enable (CE)
input to cascade several stages. CE disables counting when in the high state. The master reset (MR) input, when
taken high, sets all the decoded outputs, except 0, to low.
The CD54HCT4017 is characterized for operation over the full military temperature range of –55°C to 125°C.
FUNCTION TABLE
INPUTS
CP CE MR
OUTPUT STATE†
LXL
No change
XHL
No change
XXH
0=H
1–9 = L
L L Increments counter
XL
No change
XL
No change
H L Increments counter
If n < 5, TC = H; otherwise, TC = L.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1999, Texas Instruments Incorporated
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
1

CD54HCT4017
CD54HCT4017
DECADE COUNTER/DIVIDER
WITH TEN DECODED OUTPUTS
SGDS012 – MAY 1999
logic diagram (positive logic)
3
0
2
1
4
2
7
3
10
4
1
5
5
6
6
7
9
8
11
9
12
TC
DQ
CQ
R
15
MR
13
CE
14
CP
DQ
CQ
R
DQ
CQ
R
DQ
CQ
R
DQ
CQ
R
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265


Features D 4.5-V to 5.5-V Operation D Fully Stati c Operation D Buffered Inputs D Common Reset D Positive-Edge Clocking D Balanc ed Propagation Delay and Transition Tim es D Direct LSTTL Input Logic Compatibi lity – VIL = 0.8 V Maximum; VIH = 2 V Minimum D CMOS Input Compatibility – II ≤ 1 µA at VOL, VOH D Packaged in Ceramic (F) DIP Packages and Also Avai lable in Chip Form (H) CD54HCT4017 DEC ADE COUNTER/DIVIDER WITH TEN DECODED OU TPUTS SGDS012 – MAY 1999 F PACKAGE (T OP VIEW) 5 1 0 2 6 7 3 GND 1 2 3 4 5 6 7 8 16 VCC 15 MR 14 CP 13 CE 12 TC 1 1 9 10 4 98 description The CD54HCT401 7 is a high-speed silicon-gate CMOS 5-s tage Johnson counter with ten decoded o utputs. Each decoded output normally is low and sequentially goes high on the low-to-high transition of the clock (CP ) input. Each output stays high for one clock period of the ten-clock-period c ycle. The terminal count (TC) output tr ansitions low to high after output ten (9) goes low, and can be used in conjunction with the clock enable (CE) .
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