DS32EL0421 FPGA-Link Serializer Datasheet

DS32EL0421 Datasheet, PDF, Equivalent


Part Number

DS32EL0421

Description

FPGA-Link Serializer

Manufacture

etcTI

Total Page 30 Pages
Datasheet
Download DS32EL0421 Datasheet


DS32EL0421
DS32EL0421, DS32ELX0421
www.ti.com
SNLS282F – MAY 2008 – REVISED APRIL 2013
DS32EL0421 , DS32ELX0421 125 - 312.5 MHz FPGA-Link Serializer with DDR LVDS
Parallel Interface
Check for Samples: DS32EL0421, DS32ELX0421
FEATURES
1
2 5-bit DDR LVDS Parallel Data Interface
• Programmable Transmit De-emphasis
• Configurable Output Levels (VOD)
• Selectable DC-balanced Encoder
• Selectable Data Scrambler
• Remote Sense for Automatic Detection and
Negotiation of Link Status
• On Chip LC VCOs
• Redundant Serial Output (ELX device only)
• Data Valid Signaling to Assist with
Synchronization of Multiple Receivers
• Supports AC- and DC-coupled Signaling
• Integrated CML and LVDS Terminations
• Configurable PLL Loop Bandwidth
• Programmable Output Termination (50or
75).
• Built-in Test Pattern Generator
• Loss of Lock and Error Reporting
• Configurable via SMBus
• 48-pin WQFN Package with Exposed DAP
TARGET APPLICATIONS
• Imaging: Industrial, Medical Security, Printers
• Displays: LED Walls, Commercial
• Video Transport
• Communication Systems
• Test and Measurement
• Industrial Bus
DESCRIPTION
The DS32EL0421/DS32ELX0421 is a 125 MHz to
312.5 MHz (DDR) serializer for high-speed serial
transmission over FR-4 printed circuit board
backplanes, balanced cables, and optical fiber. This
easy-to-use chipset integrates advanced signal and
clock conditioning functions, with an FPGA friendly
interface.
The DS32EL0421/DS32ELX0421 serializes up to 5
parallel input LVDS channels to create a maximum
data payload of 3.125 Gbps. If the integrated DC-
balance encoding is enabled, the maximum data
payload achievable is 2.5 Gbps.
The DS32EL0421/DS32ELX0421 serializers feature
remote sense capability to automatically detect and
negotiate link status with its companion
DS32EL0124/DS32ELX0124 deserializers without
requiring an additional feedback path.
The parallel LVDS interface reduces FPGA I/O pins,
board trace count and alleviates EMI issues, when
compared to traditional single-ended wide bus
interfaces.
The DS32EL0421/DS32ELX0421 is programmable
through a SMBus interface as well as through control
pins.
KEY SPECIFICATIONS
• 1.25 to 3.125 Gbps Serial Data Rate
• 125 to 312.5 MHz DDR Parallel Clock
• -40° to +85°C Temperature Range
• >8 kV ESD (HBM) Protection
• Low Intrinsic Jitter — 35ps at 3.125 Gbps
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2013, Texas Instruments Incorporated

DS32EL0421
DS32EL0421, DS32ELX0421
SNLS282F – MAY 2008 – REVISED APRIL 2013
Typical Application
FPGA
DS32ELX0421
DS32ELX0124
www.ti.com
FPGA
5 LVDS
LVDS
Clock
Control
SMBus
Connection Diagram
3.125 Gbps Data Payload
D0 R0
D1
Redundant
Driver
Redundant Link
Retimed
Output
R1
RT0
PLL Control
PLL Control
5 LVDS
LVDS
Clock
SMBus
Control
VDD33 1
N/C 2
GPIO0 3
GPIO1 4
DC_B 5
RS 6
VDD25 7
N/C 8
DE_EMPH0 9
DE_EMPH1 10
GPIO2 11
N/C 12
49 DAP = GND
DS32EL0421
36 VDD33
35 VDD25
34 SMB_CS
33 SCK
32 SDA
31 LOCK
30 RESET
29 RSVD
28 VDDPLL
27 LF_CP
26 LF_REF
25 VDD25
See Package Number RHS0048A
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Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: DS32EL0421 DS32ELX0421


Features DS32EL0421, DS32ELX0421 www.ti.com SNL S282F – MAY 2008 – REVISED APRIL 20 13 DS32EL0421 , DS32ELX0421 125 - 312. 5 MHz FPGA-Link Serializer with DDR LVD S Parallel Interface Check for Samples: DS32EL0421, DS32ELX0421 FEATURES 1 2 5-bit DDR LVDS Parallel Data Interfa ce • Programmable Transmit De-emphasi s • Configurable Output Levels (VOD) • Selectable DC-balanced Encoder • Selectable Data Scrambler • Remote Se nse for Automatic Detection and Negotia tion of Link Status • On Chip LC VCOs • Redundant Serial Output (ELX devic e only) • Data Valid Signaling to Ass ist with Synchronization of Multiple Re ceivers • Supports AC- and DC-coupled Signaling • Integrated CML and LVDS Terminations • Configurable PLL Loop Bandwidth • Programmable Output Termi nation (50Ω or 75Ω). • Built-in T est Pattern Generator • Loss of Lock and Error Reporting • Configurable vi a SMBus • 48-pin WQFN Package with Ex posed DAP TARGET APPLICATIONS • Imaging: Industrial, Medical Security, Printers • Displays: LED Walls, Co.
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