DS90C032 Line Receiver Datasheet

DS90C032 Datasheet, PDF, Equivalent


Part Number

DS90C032

Description

LVDS Quad CMOS Differential Line Receiver

Manufacture

etcTI

Total Page 18 Pages
Datasheet
Download DS90C032 Datasheet


DS90C032
DS90C032
www.ti.com
SNLS094D – JUNE 1998 – REVISED APRIL 2013
DS90C032 LVDS Quad CMOS Differential Line Receiver
Check for Samples: DS90C032
FEATURES
1
2 >155.5 Mbps (77.7 MHz) switching rates
• Accepts small swing (350 mV) differential
signal levels
• Ultra low power dissipation
• 600 ps maximum differential skew (5V, 25°C)
• 6.0 ns maximum propagation delay
• Industrial operating temperature range
• Military operating temperature range option
• Available in surface mount packaging (SOIC)
and (LCCC)
• Pin compatible with DS26C32A, MB570
(PECL), and 41LF (PECL)
• Supports OPEN input fail-safe
• Supports short and terminated input fail-safe
with the addition of external failsafe biasing
• Compatible with IEEE 1596.3 SCI LVDS
standard
• Conforms to ANSI/TIA/EIA-644 LVDS standard
• Available to Standard Microcircuit Drawing
(SMD) 5962-95834
DESCRIPTION
TheDS90C032 is a quad CMOS differential line
receiver designed for applications requiring ultra low
power dissipation and high data rates. The device
supports data rates in excess of 155.5 Mbps (77.7
MHz) and uses Low Voltage Differential Signaling
(LVDS) technology.
TheDS90C032 accepts low voltage (350 mV)
differential input signals and translates them to
CMOS (TTL compatible) output levels. The receiver
supports a TRI-STATE function that may be used to
multiplex outputs. The receiver also supports OPEN,
shorted, and terminated (100Ω) input Failsafe with
the addition of external failsafe biasing. Receiver
output will be HIGH for both Failsafe conditions.
TheDS90C032 and companion line driver
(DS90C031) provide a new alternative to high power
pseudo-ECL devices for high speed point-to-point
interface applications.
Connection Diagram
Dual-In-Line
Figure 1. See Package Number D (R-PDSO-G16)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1998–2013, Texas Instruments Incorporated

DS90C032
DS90C032
SNLS094D – JUNE 1998 – REVISED APRIL 2013
Functional Diagram and Truth Table
www.ti.com
Receiver
ENABLES
EN EN*
LH
All other combinations of
ENABLE inputs
INPUTS
RIN+ RIN
X
VID 0.1V
VID ≤ −0.1V
Full Fail-safe
OPEN/SHORT or
Terminated
OUTPUT
ROUT
Z
H
L
H
2 Submit Documentation Feedback
Product Folder Links: DS90C032
Copyright © 1998–2013, Texas Instruments Incorporated


Features DS90C032 www.ti.com SNLS094D – JUNE 1998 – REVISED APRIL 2013 DS90C032 L VDS Quad CMOS Differential Line Receive r Check for Samples: DS90C032 FEATURES 1 •2 >155.5 Mbps (77.7 MHz) switchin g rates • Accepts small swing (350 mV ) differential signal levels • Ultra low power dissipation • 600 ps maximu m differential skew (5V, 25°C) • 6.0 ns maximum propagation delay • Indus trial operating temperature range • M ilitary operating temperature range opt ion • Available in surface mount pack aging (SOIC) and (LCCC) • Pin compati ble with DS26C32A, MB570 (PECL), and 41 LF (PECL) • Supports OPEN input fail- safe • Supports short and terminated input fail-safe with the addition of ex ternal failsafe biasing • Compatible with IEEE 1596.3 SCI LVDS standard • Conforms to ANSI/TIA/EIA-644 LVDS stand ard • Available to Standard Microcirc uit Drawing (SMD) 5962-95834 DESCRIPTI ON TheDS90C032 is a quad CMOS different ial line receiver designed for applications requiring ultra low power dissipation and high data .
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