DS90C032B Line Receiver Datasheet

DS90C032B Datasheet, PDF, Equivalent


Part Number

DS90C032B

Description

LVDS Quad CMOS Differential Line Receiver

Manufacture

etcTI

Total Page 16 Pages
Datasheet
Download DS90C032B Datasheet


DS90C032B
DS90C032B
www.ti.com
SNLS052C – MARCH 1999 – REVISED APRIL 2013
DS90C032B LVDS Quad CMOS Differential Line Receiver
Check for Samples: DS90C032B
FEATURES
1
2 >155.5 Mbps (77.7 MHz) Switching Rates
• Accepts Small Swing (350 mV) Differential
Signal Levels
• High Impedance LVDS Inputs with Power
Down
• Ultra Low Power Dissipation
• 600 ps Maximum Differential Skew (5V, 25°C)
• 6.0 ns Maximum Propagation Delay
• Industrial Operating Temperature Range
• Available in Surface Mount Packaging (SOIC)
• Pin Compatible with DS26C32A, MB570 (PECL)
and 41LF (PECL)
• Supports OPEN and Terminated Input Failsafe
• Conforms to ANSI/TIA/EIA-644 LVDS Standard
DESCRIPTION
The DS90C032B is a quad CMOS differential line
receiver designed for applications requiring ultra low
power dissipation and high data rates. The device
supports data rates in excess of 155.5 Mbps
(77.7 MHz) and uses Low Voltage Differential
Signaling (LVDS) technology.
The DS90C032B accepts low voltage (350 mV)
differential input signals and translates them to
CMOS (TTL compatible) output levels. The receiver
supports a TRI-STATE function that may be used to
multiplex outputs. The receiver also supports OPEN
Failsafe and terminated (100Ω) input Failsafe with the
addition of external failsafe biasing. Receiver output
will be HIGH for both Failsafe conditions.
The DS90C032B provides power-off high impedance
LVDS inputs. This feature assures minimal loading
effect on the LVDS bus lines when VCC is not
present.
The DS90C032B and companion line driver
(DS90C031B) provide a new alternative to high
power pseudo-ECL devices for high-speed point-to-
point interface applications.
Connection Diagram
Functional Diagram
Figure 1. Dual-In-Line Top View
See Package Number D (R-PDSO-G16)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2013, Texas Instruments Incorporated

DS90C032B
DS90C032B
SNLS052C – MARCH 1999 – REVISED APRIL 2013
Table 1. Receiver Truth Table
ENABLES
EN EN*
LH
All other combinations of ENABLE inputs
INPUTS
RIN+ RIN
X
VID 0.1V
VID ≤ −0.1V
Failsafe OPEN or Terminated
www.ti.com
OUTPUT
ROUT
Z
H
L
H
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)
Supply Voltage (VCC)
Input Voltage (RIN+, RIN)
Enable Input Voltage (EN, EN*)
Output Voltage (ROUT)
Maximum Package Power Dissipation at +25°C
Derate Power Dissipation
Storage Temperature Range
Maximum Lead Temperature, Soldering (4 seconds)
Maximum Junction Temperature
ESD Ratings
HBM, 1.5 kΩ, 100 pF
EIAJ, 0 Ω, 200 pF
0.3V to +6V
0.3V to +5.8V
0.3V to (VCC + 0.3V)
0.3V to (VCC + 0.3V)
1025 mW
8.2 mW/°C above +25°C
65°C to +150°C
+260°C
+150°C
2kV
250V
(1) “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be ensured. They are not meant to imply
that the devices should be operated at these limits. “Electrical Characteristics” specifies conditions of device operation.
Recommended Operating Conditions
Supply Voltage (VCC)
Receiver Input Voltage
Operating Free Air Temperature (TA)
Min Typ Max Units
+4.5 +5.0 +5.5
V
GND
2.4 V
40 +25 +85
°C
2 Submit Documentation Feedback
Product Folder Links: DS90C032B
Copyright © 1999–2013, Texas Instruments Incorporated


Features DS90C032B www.ti.com SNLS052C – MARC H 1999 – REVISED APRIL 2013 DS90C032 B LVDS Quad CMOS Differential Line Rece iver Check for Samples: DS90C032B FEAT URES 1 •2 >155.5 Mbps (77.7 MHz) Swit ching Rates • Accepts Small Swing (35 0 mV) Differential Signal Levels • Hi gh Impedance LVDS Inputs with Power Dow n • Ultra Low Power Dissipation • 6 00 ps Maximum Differential Skew (5V, 25 °C) • 6.0 ns Maximum Propagation Del ay • Industrial Operating Temperature Range • Available in Surface Mount P ackaging (SOIC) • Pin Compatible with DS26C32A, MB570 (PECL) and 41LF (PECL) • Supports OPEN and Terminated Input Failsafe • Conforms to ANSI/TIA/EIA- 644 LVDS Standard DESCRIPTION The DS90 C032B is a quad CMOS differential line receiver designed for applications requ iring ultra low power dissipation and h igh data rates. The device supports dat a rates in excess of 155.5 Mbps (77.7 M Hz) and uses Low Voltage Differential S ignaling (LVDS) technology. The DS90C032B accepts low voltage (350 mV) differential input .
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