DS90C124 II Serializer/Deserializer Datasheet

DS90C124 Datasheet, PDF, Equivalent


Part Number

DS90C124

Description

5-MHz to 35-MHz DC-Balanced 24-Bit FPD-Link II Serializer/Deserializer

Manufacture

etcTI

Total Page 30 Pages
Datasheet
Download DS90C124 Datasheet


DS90C124
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DS90C124, DS90C241
SNLS209M – NOVEMBER 2005 – REVISED JANUARY 2017
DS90C241 and DS90C124 5-MHz to 35-MHz DC-Balanced 24-Bit
FPD-Link II Serializer and Deserializer
1 Features
1 5-MHz to 35-MHz Clock Embedded and DC-
Balancing 24:1 and 1:24 Data Transmissions
• User Defined Pre-Emphasis Driving Ability
Through External Resistor on LVDS Outputs and
Capable to Drive Up to 10-Meter Shielded
Twisted-Pair Cable
• User-Selectable Clock Edge for Parallel Data on
Both Transmitter and Receiver
• Internal DC Balancing Encode and Decode
(Supports AC-Coupling Interface With No External
Coding Required)
• Individual Power-Down Controls for Both
Transmitter and Receiver
• Embedded Clock CDR (Clock and Data Recovery)
on Receiver and No External Source of Reference
Clock Required
• All Codes RDL (Random Data Lock) to Support
Live-Pluggable Applications
• LOCK Output Flag to Ensure Data Integrity at
Receiver Side
• Balanced TSETUP and THOLD Between RCLK and
RDATA on Receiver Side
• PTO (Progressive Turnon) LVCMOS Outputs to
Reduce EMI and Minimize SSO Effects
• All LVCMOS Inputs and Control Pins Have
Internal Pulldown
• On-Chip Filters for PLLs on Transmitter and
Receiver
• Temperature Range: –40°C to 105°C
• Greater Than 8-kV HBM ESD Tolerant
• Meets AEC-Q100 Compliance
• Power Supply Range: 3.3 V ± 10%
• 48-Pin TQFP Package
2 Applications
• Automotive Central Information Displays
• Automotive Instrument Cluster Displays
• Automotive Heads-Up Displays
• Remote Camera-Based Driver Assistance
Systems
3 Description
The DS90C241 and DS90C124 chipset translates a
24-bit parallel bus into a fully transparent data and
control LVDS serial stream with embedded clock
information. This single serial stream simplifies
transferring a 24-bit bus over PCB traces or over
cable by eliminating the skew problems between
parallel data and clock paths. It saves system cost by
narrowing data paths, which in turn reduces PCB
layers, cable width, and connector size and pins.
The DS90C241 and DS90C124 incorporate LVDS
signaling on the high-speed I/O. LVDS provides a
low-power and low-noise environment for reliably
transferring data over a serial transmission path. By
optimizing the serializer output edge rate for the
operating frequency range, EMI is further reduced.
In addition, the device features pre-emphasis to boost
signals over longer distances using lossy cables.
Internal DC balanced encoding and decoding
supports AC-coupled interconnects.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
DS90C124
DS90C241
TQFP (48)
7.00 mm x 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
PRE
DEN
VODSEL
Block Diagram
REN
24
DIN
TRFB
DOUT+
RIN+
DOUT-
RIN-
24
ROUT
TCLK
TPWDNB
PLL
Timing
and
Control
RRFB
RPWDNB
PLL Timing
and
Control
Clock
Recovery
LOCK
RCLK
SERIALIZER ± DS90C241
DESERIALIZER ± DS90C124
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

DS90C124
DS90C124, DS90C241
SNLS209M – NOVEMBER 2005 – REVISED JANUARY 2017
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 7
6.1 Absolute Maximum Ratings ..................................... 7
6.2 ESD Ratings.............................................................. 7
6.3 Recommended Operating Conditions....................... 7
6.4 Thermal Information .................................................. 8
6.5 Electrical Characteristics........................................... 8
6.6 Timing Requirements – Serializer............................. 9
6.7 Switching Characteristics – Serializer..................... 10
6.8 Switching Characteristics – Deserializer................. 10
6.9 Typical Characteristics ............................................ 11
7 Parameter Measurement Information ................ 12
8 Detailed Description ............................................ 17
8.1 Overview ................................................................. 17
8.2 Functional Block Diagram ....................................... 17
8.3 Feature Description................................................. 17
8.4 Device Functional Modes........................................ 20
9 Applications and Implementation ...................... 22
9.1 Application Information............................................ 22
9.2 Typical Application ................................................. 22
10 Power Supply Recommendations ..................... 27
11 Layout................................................................... 28
11.1 Layout Guidelines ................................................. 28
11.2 Layout Example .................................................... 29
12 Device and Documentation Support ................. 32
12.1 Documentation Support ........................................ 32
12.2 Related Links ........................................................ 32
12.3 Receiving Notification of Documentation Updates 32
12.4 Community Resources.......................................... 32
12.5 Trademarks ........................................................... 32
12.6 Electrostatic Discharge Caution ............................ 32
12.7 Glossary ................................................................ 32
13 Mechanical, Packaging, and Orderable
Information ........................................................... 33
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision L (April 2013) to Revision M
Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
• Deleted Lead temperature, soldering (260°C maximum) from Absolute Maximum Ratings.................................................. 7
• Added Thermal Information table ........................................................................................................................................... 8
• Added Typical Characteristics (PCLK = 5 MHz and PCLK = 25 MHz plus pre-emphasis).................................................. 11
Changes from Revision K (April 2013) to Revision L
Page
• Changed layout of National Semiconductor Data Sheet to TI format .................................................................................... 1
2 Submit Documentation Feedback
Copyright © 2005–2017, Texas Instruments Incorporated
Product Folder Links: DS90C124 DS90C241


Features Product Folder Order Now Technical Doc uments Tools & Software Support & Com munity DS90C124, DS90C241 SNLS209M – NOVEMBER 2005 – REVISED JANUARY 2017 DS90C241 and DS90C124 5-MHz to 35-MHz DC-Balanced 24-Bit FPD-Link II Serializ er and Deserializer 1 Features •1 5- MHz to 35-MHz Clock Embedded and DCBala ncing 24:1 and 1:24 Data Transmissions • User Defined Pre-Emphasis Driving A bility Through External Resistor on LVD S Outputs and Capable to Drive Up to 10 -Meter Shielded Twisted-Pair Cable • User-Selectable Clock Edge for Parallel Data on Both Transmitter and Receiver • Internal DC Balancing Encode and De code (Supports AC-Coupling Interface Wi th No External Coding Required) • Ind ividual Power-Down Controls for Both Tr ansmitter and Receiver • Embedded Clo ck CDR (Clock and Data Recovery) on Rec eiver and No External Source of Referen ce Clock Required • All Codes RDL (Ra ndom Data Lock) to Support Live-Pluggab le Applications • LOCK Output Flag to Ensure Data Integrity at Receiver Side • Ba.
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