DS90C3202 FPD-Link Receiver Datasheet

DS90C3202 Datasheet, PDF, Equivalent


Part Number

DS90C3202

Description

3.3V 8 MHz to 135 MHz Dual FPD-Link Receiver

Manufacture

etcTI

Total Page 26 Pages
Datasheet
Download DS90C3202 Datasheet


DS90C3202
DS90C3202
www.ti.com
SNLS191D – APRIL 2005 – REVISED APRIL 2013
DS90C3202 3.3V 8 MHz to 135 MHz Dual FPD-Link Receiver
Check for Samples: DS90C3202
FEATURES
1
2 Up to 9.45 Gbit/s data throughput
• 8 MHz to 135 MHz input clock support
• Supports up to QXGA panel resolutions
• Supports HDTV panel resolutions and frame
rates up to 1920 x 1080p
• LVDS 30-bit, 24-bit or 18-bit color data inputs
• Supports single pixel and dual pixel interfaces
• Supports spread spectrum clocking
• Two-wire serial communication interface
• Programmable clock edge and control strobe
select
• Power down mode
• +3.3V supply voltage
• 128-pin TQFP Package
• Compliant to TIA/EIA-644-A-2001 LVDS
Standard
DESCRIPTION
The DS90C3202 is a 3.3V single/dual FPD-Link 10-
bit color receiver is designed to be used in Liquid
Crystal Display TVs, LCD Monitors, Digital TVs, and
Plasma Display Panel TVs. The DS90C3202 is
designed to interface between the digital video
processor and the display device using the low-
power, low-EMI LVDS (Low Voltage Differential
Signaling) interface. The DS90C3202 converts up to
ten LVDS data streams back into 70 bits of parallel
LVCMOS/LVTTL data. The receiver can be
programmed with rising edge or falling edge clock.
Optional wo-wire serial programming allows fine
tuning in development and production environments.
With an input clock at 135 MHz, the maximum
transmission rate of each LVDS line is 945 Mbps, for
an aggregate throughput rate of 9.45 Gbps (945
Mbytes/s). This allows the dual 10-bit LVDS Receiver
to support resolutions up to HDTV.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2013, Texas Instruments Incorporated

DS90C3202
DS90C3202
SNLS191D – APRIL 2005 – REVISED APRIL 2013
Block Diagram
RXOA-/+
RXOB-/+
RXOC-/+
RXOD-/+
RXOE-/+
RXEA-/+
RXEB-/+
RXEC-/+
RXED-/+
RXEE-/+
7
RXOA[6:0]
7
RXOB[6:0]
7
RXOC[6:0]
7
RXOD[6:0]
7
RXOE[6:0]
7
RXEA[6:0]
7
RXEB[6:0]
7
RXEC[6:0]
7
RXED[6:0]
7
RXEE[6:0]
RCLKIN-/+
RFB
PWDNB
MODE0
MODE1
S2CLK
S2DAT
PLL RCLKOUT
Figure 1. Receiver Block Diagram
Typical Application Diagram
Host
(PC, Graphics Board, Video Processor)
Video
Source
DE
Pixel Data
Clock
HSYNC
VSYNC
DS90C3201
FPD-Link
Transmitter
LVDS
5 Pairs
5 Pairs
LVDS Clock
2-Wire Serial
Interface
Display
(LCD Monitor, LCD TV, Digital TV)
DS90C3202
FPD-Link
Receiver
DE
Pixel Data
Clock
HSYNC
VSYNC
Digital
Display
www.ti.com
Figure 2. LCD Panel Application Diagram
Functional Description
The DS90C3201 and DS90C3202 are a dual 10-bit color Transmitter and Receiver FPD-Link chipset designed to
transmit data at clocks speeds from 8 to 135 MHz. DS90C3201 and DS90C3202 are designed to interface
between the digital video processor and the display using a LVDS interface. The DS90C3201 transmitter
serializes 2 channels of video data (10-bit each for RGB for each channel, totaling 60 bits) and control signals
(HSYNC, VSYNC, DE and two user-defined signals) along with clock signal to 10 channels of LVDS signals and
transmits them. The DS90C3202 receiver converts 10 channels of LVDS signals into parallel signals and outputs
2 Submit Documentation Feedback
Product Folder Links: DS90C3202
Copyright © 2005–2013, Texas Instruments Incorporated


Features DS90C3202 www.ti.com SNLS191D – APRI L 2005 – REVISED APRIL 2013 DS90C320 2 3.3V 8 MHz to 135 MHz Dual FPD-Link R eceiver Check for Samples: DS90C3202 F EATURES 1 •2 Up to 9.45 Gbit/s data t hroughput • 8 MHz to 135 MHz input cl ock support • Supports up to QXGA pan el resolutions • Supports HDTV panel resolutions and frame rates up to 1920 x 1080p • LVDS 30-bit, 24-bit or 18-b it color data inputs • Supports singl e pixel and dual pixel interfaces • S upports spread spectrum clocking • Tw o-wire serial communication interface Programmable clock edge and control strobe select • Power down mode • + 3.3V supply voltage • 128-pin TQFP Pa ckage • Compliant to TIA/EIA-644-A-20 01 LVDS Standard DESCRIPTION The DS90C 3202 is a 3.3V single/dual FPD-Link 10b it color receiver is designed to be use d in Liquid Crystal Display TVs, LCD Mo nitors, Digital TVs, and Plasma Display Panel TVs. The DS90C3202 is designed t o interface between the digital video processor and the display device using the lowpower, lo.
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