DS90C365A LVDS Transmitter Datasheet

DS90C365A Datasheet, PDF, Equivalent


Part Number

DS90C365A

Description

+3.3V Programmable LVDS Transmitter

Manufacture

etcTI

Total Page 17 Pages
Datasheet
Download DS90C365A Datasheet


DS90C365A
DS90C365A
www.ti.com
SNLS181I – APRIL 2004 – REVISED APRIL 2013
+3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display Link-87.5 MHz
Check for Samples: DS90C365A
FEATURES
1
23 Pin-to-pin compatible to DS90C363,
DS90C363A and DS90C365
• No special start-up sequence required
between clock/data and /PD pins. Input signals
(clock and data) can be applied either before
or after the device is powered.
• Support Spread Spectrum Clocking up to
100kHz frequency modulation & deviations of
±2.5% center spread or -5% down spread.
• “Input Clock Detection” feature will pull all
LVDS pairs to logic low when input clock is
missing and when /PD pin is logic high.
• 18 to 87.5 MHz shift clock support
• Tx power consumption < 146 mW (typ) at 87.5
MHz Grayscale
• Tx Power-down mode < 37 uW (typ)
• Supports VGA, SVGA, XGA, SXGA (dual pixel),
SXGA+ (dual pixel), UXGA (dual pixel).
• Narrow bus reduces cable size and cost
• Up to 1.785 Gbps throughput
• Up to 223.125 Megabytes/sec bandwidth
• 345 mV (typ) swing LVDS devices for low EMI
• PLL requires no external components
• Compliant to TIA/EIA-644 LVDS standard
• Low profile 48-lead TSSOP package
DESCRIPTION
The DS90C365A is a pin to pin compatible
replacement for DS90C363, DS90C363A and
DS90C365. The DS90C365A has additional features
and improvements making it an ideal replacement for
DS90C363, DS90C363A and DS90C365. family of
LVDS Transmitters.
The DS90C365A transmitter converts 21 bits of
LVCMOS/LVTTL data into four LVDS (Low Voltage
Differential Signaling) data streams. A phase-locked
transmit clock is transmitted in parallel with the data
streams over the fourth LVDS link. Every cycle of the
transmit clock 21 bits RGB of input data are sampled
and transmitted. At a transmit clock frequency of 87.5
MHz, 21 bits of RGB data and 3 bits of LCD timing
and control data (FPLINE, FPFRAME, DRDY) are
transmitted at a rate of 612.5 Mbps per LVDS data
channel. Using a 87.5 MHz clock, the data throughput
is 229.687 Mbytes/sec. This transmitter can be
programmed for Rising edge strobe or Falling edge
strobe through a dedicated pin. A Rising edge or
Falling edge strobe transmitter will interoperate with a
Falling edge strobe FPDLink Receiver without any
translation logic.
This chipset is an ideal means to solve EMI and
cable size problems associated with wide, high-speed
TTL interfaces with added Spead Spectrum Clocking
support..
Block Diagram
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TRI-STATE is a registered trademark of Texas Instruments.
2
All other trademarks are the property of their respective owners.
3
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2013, Texas Instruments Incorporated

DS90C365A
DS90C365A
SNLS181I – APRIL 2004 – REVISED APRIL 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)
Supply Voltage (VCC)
CMOS/TTL Input Voltage
LVDS Driver Output Voltage
LVDS Output Short Circuit Duration
Junction Temperature
Storage Temperature
Lead Temperature (Soldering, 4 seconds)
Maximum Package Power Dissipation Capacity at 25°C, TSSOP Package
Package Derating
ESD Rating
HBM, 1.5k, 100pF
EIAJ, 0, 200 pF
Latch Up Tolerance at 25°C
0.3V to +4V
0.5V to (VCC + 0.3)V
0.3V to (VCC + 0.3)V
Continuous
+150°C
65°C to +150°C
+260°C
1.98W
16 mW/°C above +25°C
7kV
500V
±100mA
(1) “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be verified. They are not meant to imply
that the device should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Recommended Operating Conditions
Supply Voltage (VCC)
Operating Free Air Temperature (TA)
Supply Noise Voltage (VCC)
TxCLKIN frequency
Min Nom Max Unit
3.0 3.3 3.6
V
10 +25 +70
°C
200 mVPP
18 85 MHz
Electrical Characteristics(1)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ (2)
Max
Unit
LVCMOS/LVTTL DC SPECIFICATIONS
VIH High Level Input Voltage
VIL Low Level Input Voltage
VCL Input Clamp Voltage
IIN Input Current
LVDS DC SPECIFICATIONS
ICL = 18 mA
VIN = 0.4V, 2.5V or VCC
VIN = GND
2.0 VCC
0 0.8
0.79
1.5
+1.8
+10
10 0
V
V
V
μA
μA
VOD
ΔVOD
VOS
ΔVOS
Differential Output Voltage
Change in VOD between
complimentary output states
Offset Voltage (3)
Change in VOS between
complimentary output states
RL = 100
250 345 450
35
1.13 1.25 1.38
35
mV
mV
V
mV
IOS
Output Short Circuit Current
VOUT = 0V, RL = 100
IOZ
Output TRI-STATE® Current
Power Down = 0V,
VOUT = 0V or V CC
3.5
±1
5
±10
mA
μA
(1) Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground
unless otherwise specified (except VOD and ΔVOD).
(2) Typical values are given for VCC = 3.3V and TA = +25°C unless specified otherwise.
(3) VOS previously referred as VCM.
2 Submit Documentation Feedback
Product Folder Links: DS90C365A
Copyright © 2004–2013, Texas Instruments Incorporated


Features DS90C365A www.ti.com SNLS181I – APRI L 2004 – REVISED APRIL 2013 +3.3V Pr ogrammable LVDS Transmitter 18-Bit Flat Panel Display Link-87.5 MHz Check for Samples: DS90C365A FEATURES 1 •23 Pi n-to-pin compatible to DS90C363, DS90C3 63A and DS90C365 • No special start-u p sequence required between clock/data and /PD pins. Input signals (clock and data) can be applied either before or a fter the device is powered. • Support Spread Spectrum Clocking up to 100kHz frequency modulation & deviations of ± 2.5% center spread or -5% down spread. • “Input Clock Detection” feature will pull all LVDS pairs to logic low when input clock is missing and when /P D pin is logic high. • 18 to 87.5 MHz shift clock support • Tx power consu mption < 146 mW (typ) at 87.5 MHz Grays cale • Tx Power-down mode < 37 uW (ty p) • Supports VGA, SVGA, XGA, SXGA (d ual pixel), SXGA+ (dual pixel), UXGA (d ual pixel). • Narrow bus reduces cabl e size and cost • Up to 1.785 Gbps throughput • Up to 223.125 Megabytes/sec bandwidth • 34.
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