DS90CF384AQ LVDS Receiver Datasheet

DS90CF384AQ Datasheet, PDF, Equivalent


Part Number

DS90CF384AQ

Description

+3.3V LVDS Receiver

Manufacture

etcTI

Total Page 18 Pages
Datasheet
Download DS90CF384AQ Datasheet


DS90CF384AQ
DS90CF384AQ
www.ti.com
SNLS345A – AUGUST 2011 – REVISED APRIL 2013
DS90CF384AQ +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link - 65 MHz
Check for Samples: DS90CF384AQ
FEATURES
1
2 Automotive Grade Device, AEC-Q100 Grade 3
Qualified
• Operating Temperature Range: –40°C to +85°C
• 20 to 65 MHz Shift Clock Support
• 50% Duty Cycle on Receiver Output Clock
• Best–in–Class Set & Hold Times on
RxOUTPUTs
• Rx Power Consumption <142 mW (typ)
@65MHz Grayscale
• Rx Power-down Mode <200μW (max)
• ESD Rating >7 kV (HBM), >700V (EIAJ)
• Supports VGA, SVGA, XGA and Dual Pixel
SXGA.
• PLL Requires No External Components
• Compatible with TIA/EIA-644 LVDS Standard
• Low Profile 56-Lead TSSOP Package
DESCRIPTION
The DS90CF384AQ receiver converts the four LVDS
data streams at up to 1.8 Gbps throughput (227
Megabytes/sec bandwidth) back into parallel 28 bits
of LVCMOS/LVTTL data. In a Display application, the
28 bits include: 24 bits of RGB data and up to 4 bits
of video control (Hsync, Vsync, DE and CNTL).
The DS90CF384AQ device is enhanced over prior
generation FPD-Link receivers, provides a wider data
valid time on the receiver output and is offered as an
AEC-Q100 grade 3 device.
FPD-Link is an ideal means to solve EMI and cable
size problems associated with wide, high speed
LVCMOS/LVTTL interfaces.
Block Diagram
Figure 1. DS90CF384AQ Block Diagram
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2013, Texas Instruments Incorporated

DS90CF384AQ
DS90CF384AQ
SNLS345A – AUGUST 2011 – REVISED APRIL 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Absolute Maximum Ratings(1)(2)
Supply Voltage (VCC)
LVCMOS/LVTTL Input Voltage
LVCMOS/LVTTL Output Voltage
LVDS Receiver Input Voltage
Junction Temperature
Storage Temperature
For soldering specifications: see http://www.ti.com/lit/SNOA549
Maximum Package Power Dissipation Capacity @ 25°C
DGG Package:
DGG Package Derating:
ESD Rating
(HBM, 1.5 k, 100 pF)
(EIAJ, 0, 200 pF)
0.3V to +4V
0.3V to (VCC + 0.3V)
0.3V to (VCC + 0.3V)
0.3V to (VCC + 0.3V)
+150°C
65°C to +150°C
1.61 W
12.4 mW/°C above +25°C
> 7 kV
> 700V
(1) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
(2) “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be ensured. They are not meant to imply
that the device should be operated at these limits. The “Electrical Characteristics” specify conditions for device operation.
Recommended OperatingConditions
Supply Voltage (VCC)
Operating Free Air
Temperature (TA )
Receiver Input Range
Supply Noise Voltage (VCC)
Min Nom Max Units
3.0 3.3 3.6
V
40 +25 +85
0 2.4
100
°C
V
mVPP
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
LVCMOS/LVTTL DC SPECIFICATIONS (For Power Down Pin)
VIH High Level Input Voltage
VIL Low Level Input Voltage
VCL Input Clamp Voltage
IIN Input Current
LVCMOS/LVTTL DC SPECIFICATIONS
ICL = 18 mA
V IN = 0.4V, 2.5V or VCC
V IN = GND
VOH High Level Output Voltage
VOL Low Level Output Voltage
IOS Output Short Circuit Current
LVDS RECEIVER DC SPECIFICATIONS
IOH = 0.4 mA
IOL = 2 mA
VOUT = 0V
VTH Differential Input High Threshold
VTL Differential Input Low Threshold
IIN Input Current
V CM = +1.2V
V IN = +2.4V, VCC = 3.6V
V IN = 0V, VCC = 3.6V
Min
2.0
GND
10
2.7
100
Typ(1) Max
0.79
+1.8
0
VCC
0.8
1.5
+10
3.3
0.06 0.3
60 120
+100
±10
±10
Units
V
V
V
μA
μA
V
V
mA
mV
mV
μA
μA
(1) Typical values are given for VCC = 3.3V and TA = +25C.
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Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: DS90CF384AQ


Features DS90CF384AQ www.ti.com SNLS345A – AU GUST 2011 – REVISED APRIL 2013 DS90C F384AQ +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link - 65 MHz Check for Samples: DS90CF384AQ FEATURES 1 2 Automotive Grade Device, AEC-Q100 G rade 3 Qualified • Operating Temperat ure Range: –40°C to +85°C • 20 to 65 MHz Shift Clock Support • 50% Dut y Cycle on Receiver Output Clock • Be st–in–Class Set & Hold Times on RxO UTPUTs • Rx Power Consumption <142 mW (typ) @65MHz Grayscale • Rx Power-do wn Mode <200μW (max) • ESD Rating >7 kV (HBM), >700V (EIAJ) • Supports VG A, SVGA, XGA and Dual Pixel SXGA. • P LL Requires No External Components • Compatible with TIA/EIA-644 LVDS Standa rd • Low Profile 56-Lead TSSOP Packag e DESCRIPTION The DS90CF384AQ receiver converts the four LVDS data streams at up to 1.8 Gbps throughput (227 Megabyt es/sec bandwidth) back into parallel 28 bits of LVCMOS/LVTTL data. In a Displa y application, the 28 bits include: 24 bits of RGB data and up to 4 bits of video control (Hsync, Vs.
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