DS90CR485 Link Serializer Datasheet

DS90CR485 Datasheet, PDF, Equivalent


Part Number

DS90CR485

Description

48-Bit Channel Link Serializer

Manufacture

etcTI

Total Page 27 Pages
Datasheet
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DS90CR485
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DS90CR485
SNLS143E – FEBRUARY 2003 – REVISED SEPTEMBER 2019
DS90CR485 133-MHz, 48-Bit Channel Link Serializer (6.384 Gbps)
1 Features
1 Up to 6.384-Gbps Throughput
• 66-MHz to 133-MHz Input Clock Support
• Reduces Cable and Connector Size and Cost
• Pre-Emphasis Reduces Cable Loading Effects
• DC Balance Reduces ISI Distortion
• 24-Bit Double Edge Inputs
• 3-V Tolerant LVCMOS/LVTTL Inputs
• Low Power, 2.5-V Supply
• Flow-Through Pinout
• 100-Pin TQFP Package
• Conforms With TIA/EIA-644-A LVDS Standard
2 Applications
• Backplane
• Cable Interconnect
3 Description
The DS90CR485 device serializes the 24
LVCMOS/LVTTL double-edge inputs (48 bits data
latched in per clock cycle) onto eight Low Voltage
Differential Signaling (LVDS) streams. A phase-
locked transmit clock is also in parallel with the data
streams over a 9th LVDS link. The reduction of the
wide TTL bus to a few LVDS lines reduces cable and
connector size and cost. The double-edge input
strobes data on both the rising and falling edges of
the clock. This minimizes the pin count required and
simplifies PCB routing between the host chip and the
serializer.
This chip can help resolve EMI and interconnect size
problems for high throughput point-to-point
applications.
The DS90CR485 is compatible with the DS90CR486
Channel-Link receiver. The device is also backward-
compatible with other Channel-Link receivers such as
the DS90CR482 and DS90CR484.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
DS90CR485
TQFP (100)
14.00 mm × 14.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Generalized Block Diagram
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

DS90CR485
DS90CR485
SNLS143E – FEBRUARY 2003 – REVISED SEPTEMBER 2019
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 7
6.1 Absolute Maximum Ratings ...................................... 7
6.2 ESD Ratings.............................................................. 7
6.3 Recommended Operating Conditions....................... 7
6.4 Thermal Information .................................................. 7
6.5 Electrical Characteristics........................................... 8
6.6 Recommended Input Requirements ......................... 8
6.7 Switching Characteristics .......................................... 8
6.8 AC Timing Diagrams................................................. 9
6.9 LVDS Interface........................................................ 12
7 Detailed Description ............................................ 15
7.1 Overview ................................................................. 15
7.2 Functional Block Diagram ....................................... 15
7.3 Feature Description................................................. 16
7.4 Device Functional Modes........................................ 18
8 Application and Implementation ........................ 20
8.1 Application Information............................................ 20
8.2 Typical Application .................................................. 20
9 Power Supply Recommendations...................... 22
9.1 Supply Bypass Recommendations ......................... 22
10 Layout................................................................... 22
10.1 Layout Guidelines ................................................. 22
10.2 Layout Example .................................................... 23
11 Device and Documentation Support ................. 24
11.1 Receiving Notification of Documentation Updates 24
11.2 Community Resources.......................................... 24
11.3 Trademarks ........................................................... 24
11.4 Electrostatic Discharge Caution ............................ 24
11.5 Glossary ................................................................ 24
12 Mechanical, Packaging, and Orderable
Information ........................................................... 24
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (March 2013) to Revision E
Page
• Added Applications section, Device Information table, Pin Configuration and Functions section, Thermal Information
table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply
Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section. ..................................................................................................................... 1
• Changed pinout and Pin Functions table .............................................................................................................................. 3
• Moved ESD ratings to ESD Ratings table .............................................................................................................................. 7
Changes from Revision C (March 2013) to Revision D
Page
• Changed layout of National Data Sheet to TI format ............................................................................................................. 1
2 Submit Documentation Feedback
Product Folder Links: DS90CR485
Copyright © 2003–2019, Texas Instruments Incorporated


Features Product Folder Order Now Technical Doc uments Tools & Software Support & Com munity DS90CR485 SNLS143E – FEBRUARY 2003 – REVISED SEPTEMBER 2019 DS90CR 485 133-MHz, 48-Bit Channel Link Serial izer (6.384 Gbps) 1 Features •1 Up t o 6.384-Gbps Throughput • 66-MHz to 1 33-MHz Input Clock Support • Reduces Cable and Connector Size and Cost • P re-Emphasis Reduces Cable Loading Effec ts • DC Balance Reduces ISI Distortio n • 24-Bit Double Edge Inputs • 3-V Tolerant LVCMOS/LVTTL Inputs • Low P ower, 2.5-V Supply • Flow-Through Pin out • 100-Pin TQFP Package • Confor ms With TIA/EIA-644-A LVDS Standard 2 A pplications • Backplane • Cable Int erconnect 3 Description The DS90CR485 device serializes the 24 LVCMOS/LVTTL d ouble-edge inputs (48 bits data latched in per clock cycle) onto eight Low Vol tage Differential Signaling (LVDS) stre ams. A phaselocked transmit clock is al so in parallel with the data streams ov er a 9th LVDS link. The reduction of the wide TTL bus to a few LVDS lines reduces cable and c.
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