Buffer Gate. SN74AHC1G126-EP Datasheet

SN74AHC1G126-EP Gate. Datasheet pdf. Equivalent

SN74AHC1G126-EP Datasheet
Recommendation SN74AHC1G126-EP Datasheet
Part SN74AHC1G126-EP
Description Single Bus Buffer Gate
Feature SN74AHC1G126-EP; SN74AHC1G126-EP www.ti.com SCLS731 – DECEMBER 2013 SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT Che.
Manufacture etcTI
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Texas Instruments SN74AHC1G126-EP
SN74AHC1G126-EP
www.ti.com
SCLS731 – DECEMBER 2013
SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT
Check for Samples: SN74AHC1G126-EP
FEATURES
1
• Operating Range of 2 V to 5.5 V
• Max tpd of 6 ns at 5 V
• Low Power Consumption, 10-μA Max ICC
• ±8-mA Output Drive at 5 V
• Latch-Up Performance Exceeds 250 mA Per
JESD 17
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
• Controlled Baseline
• One Assembly and Test Site
• One Fabrication Site
• Available in Military (–55°C to 125°C)
Temperature Range
• Extended Product Life Cycle
• Extended Product-Change Notification
• Product Traceability
DCK PACKAGE
(TOP VIEW)
OE 1
A2
5 VCC
GND 3
4Y
DESCRIPTION
The SN74AHC1G126 is a single bus buffer gate and line driver with 3-state output. The output is disabled when
the output-enable (OE) input is low. When OE is high, true data is passed from the A input to the Y output.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
TJ
–55°C to 125°C
ORDERING INFORMATION(1)
PACKAGE (2)
ORDERABLE PART NUMBER
SOT (SC-70) – DCK
Reel of 250
74AHC1G126MDCKTEP
TOP-SIDE MARKING
SLI
VID NUMBER
V62/14605-01XE
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
Table 1. FUNCTION TABLE
INPUTS
OE A
HH
HL
LX
OUTPUT
Y
H
L
Z
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated



Texas Instruments SN74AHC1G126-EP
SN74AHC1G126-EP
SCLS731 – DECEMBER 2013
LOGIC DIAGRAM (POSITIVE LOGIC)
1
OE
2
A
4
Y
www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)
over operating junction temperature range (unless otherwise noted)
VCC Supply voltage range
VI Input voltage range(2)
VO Output voltage range(2)
IIK Input clamp current
IOK Output clamp current
IO Continuous output current
Continuous current through VCC or GND
TJ Junction temperature range
Tstg Storage temperature range
VI < 0
VO < 0 or VO > VCC
VO = 0 to VCC
0.5 V to 7 V
0.5 V to 7 V
0.5 V to VCC + 0.5 V
-20 mA
±20 mA
±25 mA
±50 mA
55°C to 150°C
65°C to 150°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
THERMAL INFORMATION
THERMAL METRIC(1)
SN74AHC1G126-EP
DCK
UNITS
θJA
θJCtop
θJB
ψJT
ψJB
θJCbot
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance(3)
Junction-to-board thermal resistance(4)
Junction-to-top characterization parameter(5)
Junction-to-board characterization parameter(6)
Junction-to-case (bottom) thermal resistance(7)
5 PINS
282.8
91.1
60.1
1.6
59.2
N/A
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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Copyright © 2013, Texas Instruments Incorporated



Texas Instruments SN74AHC1G126-EP
SN74AHC1G126-EP
www.ti.com
SCLS731 – DECEMBER 2013
RECOMMENDED OPERATING CONDITIONS(1)
MIN MAX
VCC Supply voltage
VIH High-level input voltage
VIL Low-level input voltage
VI Input voltage
VO Output voltage
IOH High-level output current
IOL Low-level output current
Δt/Δv
TJ
Input transition rise/fall time
Operating junction temperature range
VCC = 2 V
VCC = 3 V
VCC = 5.5 V
VCC = 2 V
VCC = 3 V
VCC = 5.5 V
VCC = 2 V
VCC = 3.3 V ±0.3 V
VCC = 5 V ±0.5 V
VCC = 2 V
VCC = 3.3 V ±0.3 V
VCC = 5 V ±0.5 V
VCC = 3.3 V ±0.3 V
VCC = 5 V ±0.5 V
2
1.5
2.1
3.85
0
0
–55
5.5
0.5
0.9
1.65
5.5
VCC
-50
-4
-8
-50
4
8
100
20
125
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
UNIT
V
V
V
V
V
µA
mA
µA
mA
ns/V
°C
ELECTRICAL CHARACTERISTICS
over recommended operating junction temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
2V
IOH = 50 μA
VOH
IOH = 4 mA
IOH = 8 mA
3V
4.5 V
3V
4.5
2V
IOH = 50 μA
VOL
IOH = 4 mA
IOH = 8 mA
II VI = 5.5 V or GND
IOZ VO = VCC or GND
ICC VI = VCC or GND, IO = 0
Ci VI = VCC or GND
3V
4.5 V
3V
4.5
0 V to 5.5 V
5.5 V
5.5 V
5V
MIN MAX UNIT
1.9
2.9
4.4 V
2.48
3.8
0.1
0.1
0.1 V
0.44
0.44
±1 µA
±2.5 µA
10 µA
10 pF
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: SN74AHC1G126-EP
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