SKEW BUFFER. MK2304-2 Datasheet

MK2304-2 BUFFER. Datasheet pdf. Equivalent

Part MK2304-2
Description LOW SKEW BUFFER
Feature ZERO DELAY, LOW SKEW BUFFER DATASHEET MK2304-2 Description The MK2304-2 is a low jitter, low skew,.
Manufacture Renesas
Datasheet
Download MK2304-2 Datasheet



MK2304-2
ZERO DELAY, LOW SKEW BUFFER
DATASHEET
MK2304-2
Description
The MK2304-2 is a low jitter, low skew, high performance
Phase Lock Loop (PLL) based zero delay buffer for high
speed applications. Based on IDT’s proprietary low jitter
PLL techniques, the device provides four low skew outputs
at speeds up to 133 MHz at 3.3 V. The MK2304-2 includes
a bank of two outputs running at 1/2X. In the zero delay
mode, the rising edge of the input clock is aligned with the
rising edges of all 4 outputs. Compared to competitive
CMOS devices, the MK2304-2 has the lowest jitter.
The MK2304-2 PLL enters a power-down state when there
are no rising edges on the REF input. In this mode, all
outputs are tri-stated and the PLL is turned off, resulting in
leass than 25 µA of current draw.
IDT manufactures the largest variety of clock generators
and buffers and is the largest clock supplier in the world.
Features
Packaged in 8 pin SOIC
Zero input-output delay
Two 1X outputs plus two 1/2X outputs
Output to output skew is less than 200 ps
Output clocks up from 10 MHz to 133 MHz at 3.3 V
Ability to generate 2X the input
Full CMOS outputs with 8 mA output drive capability at
TTL levels at 3.3 V
Spread SmartTM technology works with spread spectrum
clock generators
Advanced, low power, sub micron CMOS process
Operating voltage of 3.3 V
Available in industial temperature operation
Pb (lead) free package
Low Standby Current
Block Diagram
VDD
1
FBIN
CLKIN
PLL
CLKA1
CLKA2
BANK
A
IDT™ ZERO DELAY, LOW SKEW BUFFER
/2
1
GND
1
CLKB1
CLKB2
BANK
B
MK2304-2
REV G 051310



MK2304-2
MK2304-2
ZERO DELAY, LOW SKEW BUFFER
Pin Assignment
REF
CLKA1
CLKA2
GND
1
2
3
4
8 FBK
7 VDD
6 CLKB2
5 CLKB1
8 Pi n ( 150 mi l ) SOI C
ZDB
Feedback Configuration Table
Feedback From
Bank A
Bank B
CLKA1:A2
CLKIN
2XCLKIN
CLKB1:B2
CLKIN/2
CLKIN
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
Pin
Name
REF
CLKA1
CLKA2
GND
CLKB1
CLKB1
VDD
FBK
Pin
Type
Input
Pin Description
Clock input. Connect to input clock source, 5 V tolerant input.
Output Clock A1 output.
Output Clock A2 output.
Power Connect to ground.
Output Clock B1 output.
Output Clock B2 output.
Power 3.3V Power Supply.
Input PLL feedback input
External Components
The Mk2304-2 requires a minimum number of external components for proper operation. Decoupling capacitors of
0.1µF should be connected between VDD and GND, as close to the part as possible. A 33series terminating
resistor should be used on each clock output to reduce reflections.
IDT™ ZERO DELAY, LOW SKEW BUFFER
2
MK2304-2 REV G 051310





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