PCM CODEC. IDT821034 Datasheet

IDT821034 CODEC. Datasheet pdf. Equivalent

IDT821034 Datasheet
Recommendation IDT821034 Datasheet
Part IDT821034
Description QUAD PCM CODEC
Feature IDT821034; QUAD PCM CODEC WITH PROGRAMMABLE GAIN IDT821034 FEATURES: • 4 channelCODEC with on-chip digital fi.
Manufacture Renesas
Datasheet
Download IDT821034 Datasheet




Renesas IDT821034
QUAD PCM CODEC WITH
PROGRAMMABLE GAIN
IDT821034
FEATURES:
4 channelCODEC with on-chip digital filters
Software Selectable A-law/µ-law companding
Programmablegainsetting
Automatic master clock frequency selection: 2.048MHz, 4.096
MHz or 8.192MHz
Flexible PCM interface with up to 128 programmable time slots,
data rate from 512 kbits/s to 8.192 Mbits/s
5 SLIC signaling pins per channel
Flexible Serial Control Interface to microcontroller
Software programmable timing modes
TTL and CMOS compatible digital I/O
Meets or exceeds ITU-T G.711 - G.714 requirements
+5 V single power supply
Low power consumption: 100mW Typ.
Operating temperature range: -40 °C to +85 °C
Packages available: 52 pin PQFP
DESCRIPTION:
The IDT821034 is a single-chip, four channel PCM CODEC with on-
chip filters and programmable gain setting. This device provides both
µ-Law and A-Law companding digital-to-analog and analog-to-digital
conversions based on ITU-T G.711 - G.714 specifications. The digital
filters in IDT821034 provides the necessary transmit and receive filtering
for voice telephone circuit to interface with time-division multiplexed
systems. The IDT821034 has a flexible PCM interface with software
selectable timing modes and independently programmable time slot for
each transmit and receive channel. It also integrates the SLIC signaling
functions through internal registers. The CODEC and SLIC control/status
registers are accessed via the Serial Control Interface.
The IDT821034 can be used in digital telecommunication applications
such as PBX, Central Office Switch, Digital Telephone and Integrated Voice/
Data Access Unit.
FUNCTIONAL BLOCK DIAGRAM
GSX0
VFXI0
VFRO0
O_0(4 - 2)
I/O_0(1 - 0)
-
+
+2.5V
A/D
Channel 0
D/A
SLIC Interface I/O
Channel 1
Channel 2
Channel 3
PCM
Interface
DX
DR
FS
BCLK
TSX
DSP
Serial
Control
Interface
CO
CI
CS
CCLK
Timing
MCLK
The IDT logo is a registered trademark of Integrated Device Technology, Inc
INDUSTRIAL TEMPERATURE RANGE
© 2003 Integrated Device Technology, Inc.
1
MAY 13, 2003
DSC-6032/3



Renesas IDT821034
IDT821034 QUAD PCM CODEC WITH PROGRAMMABLE GAIN
PIN CONFIGURATIONS
INDUSTRIAL TEMPERATURE RANGE
GNDA
GNDA
VFXI1
GSX1
VFRO1
VDDA
GNDA
VDDA
VFRO2
GSX2
VFXI2
GNDA
GNDA
40
41
42
43
44
45
46
47
48
49
50
51
52
52-Pin PQFP
26 I/O0_0
25 GND
24 CS
23 CI
22 CO
21 CCLK
20 BCLK
19 MCLK
18 FS
17 TSX
16 DR
15 VDD
14 DX
PIN DESCRIPTION
Name
GNDA
VDDA
Type Pin Number
-- 46
51
52
40
41
-- 47
45
VFRO3
VFRO2
VFRO1
VFRO0
GSX3
GSX2
GSX1
GSX0
VFXI3
VFXI2
VFXI1
VFXI0
O3_4
O3_3
O3_2
O2_4
O2_3
O2_2
O
O
I
O
O
3
48
44
37
2
49
43
38
1
50
42
39
9
10
11
4
5
6
Description
Analog Ground.
All ground pins should be connected to the ground plane of the circuit board.
+5 V Analog Power Supply.
This pin should be bypassed to ground using 0.1µF capacitor. All power supply pins should be connected to
the power plane of the circuit board.
Voice Frequency Receiver Output.
This is the output of receive power amplifier. It can drive 2000 (or greater) load.
Gain Setting Transmit Amplifier Output.
This pin is the output of the gain setting amplifier, and the input to the differential transmit filter. It should be
connected to the corresponding VFXI pin through a resistive network to set the transmit gain. Refer to Figure
5 for details.
Voice Frequency Transmitter Input.
This pin is the input to the gain setting amplifier in the transmit path.
SLIC Signaling Output for Channel 3.
SLIC Signaling Output for Channel 2.
2



Renesas IDT821034
IDT821034 QUAD PCM CODEC WITH PROGRAMMABLE GAIN
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTION (CONTINUED)
Name
O1_4
O1_3
O1_2
O0_4
O0_3
O0_2
I/O3_1
I/O3_0
I/O2_1
I/O2_0
I/O1_1
I/O1_0
I/O0_1
I/O0_0
DX
VDD
DR
TSX
FS
MCLK
BCLK
CCLK
CO
CI
CS
GND
CNF
Type Pin Number
Description
35 SLIC Signaling Output for Channel 1.
O 34
33
30 SLIC Signaling Output for Channel 0.
O 29
28
I/O
12 SLIC Signaling I/O for Channel 3.
13
I/O
7 SLIC Signaling I/O for Channel 2.
8
I/O
32 SLIC Signaling I/O for Channel 1.
31
I/O
27 SLIC Signaling I/O for Channel 0.
26
O
14
Transmit PCM Data Output.
PCM data is shifted out of DX on rising edges of BCLK.
--
15
+5 V Digital Power Supply.
All power supply pins should be connected to the power plane of the circuit board.
I
16
Receive PCM Data Input.
PCM data is shifted into DR on falling edges of BCLK.
Time Slot Indicator Output, Open Drain
O 17 This pin pulses low during the active time slot of each channel. A low level on this pin indicates active DX
output.
Frame Synchronization.
I 18 The FS pulse serves as the reference to time slots. The width of the FS pulse should be at least one BCLK
cycle.
Master Clock.
I 19 Master Clock provides the clock for DSP. It can be 2.048 MHz, 4.096 MHz or 8.192 MHz. It must be
synchronous to FS.
Bit Clock.
I 20 Bit Clock shifts out PCM data on DX pin and shifts in PCM data on DR pin. The clock can vary from 512 kHz
to 8.192 MHz at 64 kHz increment, depending on the time slot requirement of the system.
I
21
Serial Control Interface Clock.
This is the clock for Serial Control Interface. It can be up to 8.192 MHz.
O
22
Serial Control Interface Data Tri-State Output.
This pin is used to monitor SLIC working status. It is in high impedance state when CS is high.
I
23
Serial Control Interface Data Input.
Data input on this pin can control both CODEC and SLIC.
I
24
Chip Select.
A low level on this pin enables the Serial Control Interface.
--
25
Ground.
All ground pins should be connected to the ground plane of the circuit board.
O
36
Capacitor For Noise Filter.
This pin should be connected to GNDA via a 0.1 µF capacitor.
3







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