DIGITAL SWITCH. IDT72V70800 Datasheet

IDT72V70800 SWITCH. Datasheet pdf. Equivalent

IDT72V70800 Datasheet
Recommendation IDT72V70800 Datasheet
Part IDT72V70800
Description TIME SLOT INTERCHANGE DIGITAL SWITCH
Feature IDT72V70800; 3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH 512 x 512 IDT72V70800 FEATURES: • 512 x 512 channel .
Manufacture Renesas
Datasheet
Download IDT72V70800 Datasheet




Renesas IDT72V70800
3.3 VOLT TIME SLOT INTERCHANGE
DIGITAL SWITCH
512 x 512
IDT72V70800
FEATURES:
512 x 512 channel non-blocking switching at 8.192 Mb/s
Per-channel variable or constant throughput delay
Automatic identification of ST-BUS®/GCI interfaces
Accepts 4 Serial Data Streams of 8.192 Mb/s
Automatic frame offset delay measurement
Per-stream frame delay offset programming
Per-channel high impedance output control
Per-channel Processor Mode
Control interface compatible to Intel/Motorola CPUs
Connection memory block programming
· Available in 64-pin Thin Plastic Quad Flatpack (TQFP) and
FUNCTIONAL BLOCK DIAGRAM
64-pin Small Thin Quad Flatpack (STQFP)
3.3V Power Supply
Operating Temperature Range -40°C to +85°C
3.3V I/O with 5V Tolerant Inputs
DESCRIPTION:
The IDT72V70800 is a non-blocking digital switch that has a capacity of
512 x 512 channels at a serial bit rate of 8.192 Mb/s. Some of the main features
are: programmable stream and channel control, Processor Mode, input offset
delay and high-impedance output control.
Per-stream input delay control is provided for managing large multi-chip
switches that transport both voice channel and concatenated data channels. In
addition, input streams can be individually calibrated for input frame offset.
VCC GND RESET
ODE
RX0
RX1
Receive
Serial Data
RX2 Streams
RX3
Loopback
Data Memory
Internal
Registers
Output
MUX
Connection
Memory
Transmit
Serial Data
Streams
TX0
TX1
TX2
TX3
Timing Unit
Microprocessor Interface
CLK F0i FE/ WFPS
HCLK
AS/ IM DS/ CS R/W / A0-A7 DTA D8-D15/
ALE R D
WR
AD0-AD7
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IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The ST-BUS® is a trademark of Mitel Corp.
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© 2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
MARCH 2003
DSC-5709/4



Renesas IDT72V70800
IDT72V70800 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 512 x 512
PIN CONFIGURATION
COMMERCIALTEMPERATURERANGE
PIN 1
GND
RX0
RX1
RX2
RX3
IC
IC
IC
IC
F0i
FE/HCLK
GND
CLK
VCC
DNC
DNC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48 D13
47 D12
46 D11
45 D10
44 D9
43 D8
42 GND
41 VCC
40 AD7
39 AD6
38 AD5
37 AD4
36 AD3
35 AD2
34 AD1
33 AD0
TQFP: 0.80 pitch, 14mm x 14mm (PN64-1, order code: PF)
STQFP: 0.50 pitch, 10mm x 10mm (PP64-1, order code: TF)
TOP VIEW
NOTES:
1. DNC - Do Not Connect
2. All I/O pins are 5V tolerant.
3. IC - Internal Connection, tie to Ground for normal operation.
5709 drw02
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Renesas IDT72V70800
IDT72V70800 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 512 x 512
COMMERCIALTEMPERATURERANGE
PIN DESCRIPTION
SYMBOL
NAME
GND Ground.
Vcc Vcc
TX0-3
TX Output 0 to 3
(Three-state Outputs)
RX0-3 RX Input 0 to 3
F0i Frame Pulse
I/O
O
I
I
FE/HCLK Frame Evaluation/
HCLK Clock
CLK Clock
RESET Device Reset
(Schmitt Trigger Input)
I
I
I
WFPS
A0-7
Wide Frame
Pulse Select
Address 0-7
DS/RD Data Strobe/Read
I
I
I
R/W / WR Read/Write / Write
I
CS
AS/ALE
IM
Chip Select
Address Strobe or
Latch Enable
CPU Interface Mode
I
I
I
AD0-7 Address/Data Bus 0 to 7 I/O
D8-15
DTA
Data Bus 8-15
Data Transfer
Acknowledgment
I/O
O
ODE Output Drive Enable
I
Ground Rail.
DESCRIPTION
+3.3 Volt Power Supply.
Serial data output stream. These streams have a data rate of 8.192 Mb/s.
Serial data input stream. These streams have a data rate of 8.192 Mb/s.
When the WFPS pin is LOW, this input accepts and automatically identifies frame synchronization signals formatted
according to ST-BUS® and GCI specifications. When the WFPS pin is HIGH, this pin accepts a negative frame
pulse which conforms to WFPS formats.
When the WFPS pin is LOW, this pin is the frame measurement input. When the WFPS pin is HIGH, the HCLK
(4.096 MHz clock) is required for frame alignment in the wide frame pulse (WFP) mode.
Serial clock for shifting data in/out on the serial streams (RX/TX 0-3). This input accepts a 16.384 MHz clock.
This input (active LOW) puts the IDT72V70800 in its reset state that clears the device internal counters, registers
and brings TX0-3 and microport data outputs to a high-impedance state. The time constant for a power
up reset circuit must be a minimum of five times the rise time of the power supply. In normal operation, the
RESET pin must be held LOW for a minimum of 100ns to reset the device.
When 1, enables the wide frame pulse (WFP) Frame Alignment interface. When 0, the device operates in
ST-BUS®/GCI mode.
When non-multiplexed CPU bus operation is selected, these lines provide the A0-A7 address lines to the internal
memories.
For Motorola multiplexed bus operation, this input is DS. This active HIGH DS input works in conjunction with CS
to enable the read and write operations. For Motorola non-multiplexed CPU bus operation, this input is DS. This
active LOW input works in conjunction with CS to enable the read and write operations. For Intel multiplexed bus
operation, this input is RD. This active LOW input sets the data bus lines (AD0-7, D8-15) as outputs.
In the cases of Motorola non-multiplexed and multiplexed bus operations, this input is R/W. This input controls
the direction of the data bus lines (AD0-7, D8-15) during a microprocessor access. For Intel multiplexed bus
operation, this input is WR. This active LOW input is used with RD to control the data bus (AD0-7) lines as inputs.
Active LOW input used by a microprocessor to activate the microprocessor port of IDT72V70800.
This input is used if multiplexed bus operation is selected via the IM input pin. For Motorola non-multiplexed
bus operation, connect this pin to ground.
When IM is HIGH, the microprocessor port is in the multiplexed mode. When IM is LOW, the microprocessor
port is in non-multiplexed mode.
These pins are the eight least significant data bits of the microprocessor port. In multiplexed mode, these pins
are also the input address bits of the microprocessor port.
These pins are the eight most significant data bits of the microprocessor port.
This active LOW output signal indicates that a data bus transfer is complete. When the bus cycle ends, this pin
drives HIGH and then goes high-impedance, allowing for faster bus cycles with a weaker pull-up resistor. A
pull-up resistor is required to hold a HIGH level when the pin is in high-impedance.
This is the output enable control for the TX0 to TX3 serial outputs. When ODE input is LOW and the OSB
bit of the IMS register is LOW, TX0-3 are in a high-impedance state. If this input is HIGH, the TX0-3
output drivers are enabled. However, each channel may still be put into a high-impedance state by using
the per channel control bit in the connection memory.
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