VERSACLOCK SYNTHESIZER. ICS343 Datasheet

ICS343 SYNTHESIZER. Datasheet pdf. Equivalent

Part ICS343
Description VERSACLOCK SYNTHESIZER
Feature DATASHEET FIELD PROGRAMMABLE TRIPLE OUTPUT SS VERSACLOCK SYNTHESIZER ICS343 Description The ICS343 .
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Datasheet
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ICS343
DATASHEET
FIELD PROGRAMMABLE TRIPLE OUTPUT SS VERSACLOCK SYNTHESIZER ICS343
Description
The ICS343 is a low cost, triple-output, field programmable
clock synthesizer. The ICS343 can generate three output
frequencies from 250 kHz to 200 MHz, using up to three
independently configurable PLLs. The outputs may employ
Spread Spectrum techniques to reduce system
electro-magnetic interference (EMI).
Using IDT’s VersaClock™ software to configure the PLL
and output, the ICS343 contains a One-Time
Programmable (OTP) ROM to allow field programmability.
Using Phase-Locked Loop (PLL) techniques, the device
runs from a standard fundamental mode, inexpensive
crystal, or clock. It can replace multiple crystals and
oscillators, saving board space and cost.
The device also has a power down feature that tri-states the
clock outputs and turns off the PLLs when the PDTS pin is
taken low.
The ICS343 is also available in factory-programmed
custom versions for high-volume applications.
Features
8-pin SOIC package (Pb-free)
Highly accurate frequency generation
M/N Multiplier PLL: M = 1...2048, N = 1...1024
Output clock frequencies up to 200 MHz
Spread spectrum capability for lower system EMI
Center or Down Spread up to 4% total
Selectable 32 kHz or 120 kHz modulation
Input crystal frequency from 5 to 27 MHz
Input clock frequency from 2 to 50 MHz
Operating voltage of 3.3 V, using advanced, low power
CMOS process
For one output clock, use the ICS341. For two output
clocks, see the ICS342. For more than three outputs, see
the ICS345 or ICS348.
Block Diagram
VDD
Crystal or
clock input
X1/ICLK
X2
OTP ROM
with PLL
Divider
Values
Crystal
Oscillator
External capacitors are
required with a crystal input.
PLL Clock Synthesis,
Spred Spectrum and
Control Circuitry
CLK1
CLK2
CLK3
GND
PDTS (both outputs and PLL)
IDT®/ ICS™ FIELD PROGRAMMABLE TRIPLE OUTPUT SS VERSACLOCK SYNTHESIZER 1
ICS343
REV M 090613



ICS343
ICS343
FIELD PROGRAMMABLE TRIPLE OUTPUT SS VERSACLOCK SYNTHESIZER
EPROM CLOCK SYNTHESIZER
Pin Assignment
Output Clock Selection Table
X1/ I CLK
VDD
GND
CLK1
1
2
3
4
8 X2
7 PDTS
6 CLK2
5 CLK3
Output
Frequency
Spread
Amount
CLK2
User
Configurable
User
Configurable
CLK2
User
Configurable
User
Configurable
CLK3
User
Configurable
User
Configurable
8-pin (150 mil) SOIC
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
Pin
Name
X1/ICLK
VDD
GND
CLK1
CLK3
CLK2
PDTS
X2
External Components
Pin
Type
XI
Power
Power
Output
Output
Output
Input
XO
Pin Description
Connect this pin to a crystal or external clock input.
Connect to +3.3 V.
Connect to ground.
Clock output. Weak internal pull-down when tri-state.
Clock output. Weak internal pull-down when tri-state.
Clock output. Weak internal pull-down when tri-state.
Powers down entire chip. Tri-states CLK outputs when low. Internal pull-up.
Connect this pin to a crystal, or float for clock input.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50trace (a commonly
used trace impedance), place a 33resistor in series with
the clock line, as close to the clock output pin as possible.
The nominal impedance of the clock output is 20.
Decoupling Capacitor
As with any high-performance mixed-signal IC, the ICS343
must be isolated from system power supply noise to perform
optimally.
capacitors must be connected from each of the pins X1 and
X2 to ground.
The value (in pF) of these crystal caps should equal (CL -6
pF)*2. In this equation, CL= crystal load capacitance in pF.
Example: For a crystal with a 16 pF load capacitance, each
crystal capacitor would be 20 pF [(16-6) x 2] = 20.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
A decoupling capacitor of 0.01µF must be connected
between VDD and the PCB ground plane.
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to ground.
These capacitors are used to adjust the stray capacitance of
the board to match the nominally required crystal load
capacitance. Because load capacitance can only be
increased in this trimming process, it is important to keep
stray capacitance to a minimum by using very short PCB
traces (and no vias) between the crystal and device. Crystal
1) The 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between the decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via. Distance of the ferrite bead and bulk decoupling
from the device is less critical.
2) The external crystal should be mounted just next to the
device with short traces. The X1 and X2 traces should not
be routed next to each other with minimum spaces, instead
they should be separated and away from other traces.
IDT® / ICS™ FIELD PROGRAMMABLE TRIPLE OUTPUT SS VERSACLOCK SYNTHESIZER 2
ICS343
REV M 090613





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