ADC. WM8950 Datasheet

WM8950 ADC. Datasheet pdf. Equivalent

Part WM8950
Description ADC
Feature WM8950 ADC with Microphone Input and Programmable Digital Filters DESCRIPTION The WM8950 is a low .
Manufacture Cirrus Logic
Datasheet
Download WM8950 Datasheet



WM8950
WM8950
ADC with Microphone Input and Programmable Digital Filters
DESCRIPTION
The WM8950 is a low power, high quality mono ADC designed
for portable applications such as Digital Still Camera, Digital
Voice Recorder or games console accessories.
The device integrates support for a differential or single ended
mic. External component requirements are reduced as no
separate microphone amplifiers are required.
Advanced Sigma Delta Converters are used along with digital
decimation filters to give high quality audio at sample rates
from 8 to 48ks/s. Additional digital filtering options are
available, to cater for application filtering such as wind noise
reduction, noise rejection, plus an advanced mixed signal ALC
function with noise gate is provided.
An on-chip PLL is provided to generate the required Master
Clock from an external reference clock. The PLL clock can
also be output if required elsewhere in the system.
The WM8950 operates at supply voltages from 2.5 to 3.6V,
although the digital supplies can operate at voltages down to
1.71V to save power. Different sections of the chip can also be
powered down under software control by way of the selectable
two or three wire control interface.
WM8950 is supplied in a very small 4x4mm QFN package,
offering high levels of functionality in minimum board area, with
high thermal performance.
FEATURES
Mono ADC:
Audio sample rates:8, 11.025, 16, 22.05, 24, 32, 44.1, 48kHz
SNR 94dB, THD -83dB (‘A’-weighted @ 8 48ks/s)
Multiple auxiliary analogue inputs
Mic Preamps:
Differential or single end Microphone Interface
- Programmable preamp gain
- Pseudo differential inputs with common mode rejection
- Programmable ALC / Noise Gate in ADC path
Low-noise bias supplied for electret microphones
OTHER FEATURES
5 band EQ
Programmable High-Pass Filter (wind noise reduction)
Fully Programmable IIR Filter (notch filter)
On-chip PLL
Low power, low voltage
- 2.5V to 3.6V (digital: 1.71V to 3.6V)
- power consumption 10mA all-on 48ks/s mode
4x4x0.9mm 24 lead QFN package
APPLICATIONS
Digital Still Camera
General Purpose low power audio ADC
Games console accessories
Voice recorders
AUX
analog
inputs
NOISY
GND
MICN
Mic
MICP
Rbias
20k
20k
DCVDD DBVDD DGND
WM8950
AGND2
AVDD2
Gains:
-12dB to +35.25dB
IP PGA
IP BOOST/MIX
ADC
ADC
Digital
Filters
5 Band
EQ
Programmable
High Pass
Filter
Automatic
Level Control
DSP Core
IIR Filter with
Programmable
Coefficients
I2S or
PCM
Interface
FRAME
ADCDAT
BCLK
TP
MICBIAS
50k 50k
4k 5k 500k 500k
PLL
CONTROL
INTERFACE
http://www.cirrus.com
Copyright Cirrus Logic, Inc., 20052016
(All Rights Reserved)
Rev 4.5
AUG ‘16



WM8950
WM8950
TABLE OF CONTENTS
DESCRIPTION....................................................................................................... 1
FEATURES ............................................................................................................ 1
APPLICATIONS..................................................................................................... 1
TABLE OF CONTENTS......................................................................................... 2
PIN CONFIGURATION .......................................................................................... 3
ORDERING INFORMATION.................................................................................. 3
PIN DESCRIPTION................................................................................................ 4
ABSOLUTE MAXIMUM RATINGS ........................................................................ 5
RECOMMENDED OPERATING CONDITIONS..................................................... 5
ELECTRICAL CHARACTERISTICS ..................................................................... 6
TERMINOLOGY ............................................................................................................... 7
SIGNAL TIMING REQUIREMENTS ...................................................................... 8
SYSTEM CLOCK TIMING................................................................................................ 8
AUDIO INTERFACE TIMING MASTER MODE ............................................................ 8
AUDIO INTERFACE TIMING SLAVE MODE................................................................ 9
CONTROL INTERFACE TIMING 3-WIRE MODE....................................................... 10
CONTROL INTERFACE TIMING 2-WIRE MODE....................................................... 11
DEVICE DESCRIPTION ...................................................................................... 12
INTRODUCTION ............................................................................................................ 12
INPUT SIGNAL PATH .................................................................................................... 13
ANALOGUE TO DIGITAL CONVERTER (ADC) ............................................................ 18
INPUT AUTOMATIC LEVEL CONTROL (ALC) ............................................................. 22
DIGITAL AUDIO INTERFACES ..................................................................................... 36
AUDIO SAMPLE RATES................................................................................................ 41
MASTER CLOCK AND PHASE LOCKED LOOP (PLL) ................................................. 42
GENERAL PURPOSE INPUT/OUTPUT ........................................................................ 44
CONTROL INTERFACE................................................................................................. 44
RESETTING THE CHIP ................................................................................................. 45
POWER SUPPLIES ....................................................................................................... 46
ADC POWER UP/DOWN SEQUENCE.......................................................................... 46
POWER MANAGEMENT ............................................................................................... 47
REGISTER MAP .................................................................................................. 49
DIGITAL FILTER CHARACTERISTICS .............................................................. 50
TERMINOLOGY ............................................................................................................. 50
ADC FILTER RESPONSES ........................................................................................... 50
DE-EMPHASIS FILTER RESPONSES .......................................................................... 51
HIGH-PASS FILTER ...................................................................................................... 52
5-BAND EQUALISER..................................................................................................... 53
APPLICATIONS INFORMATION ........................................................................ 57
RECOMMENDED EXTERNAL COMPONENTS ............................................................ 57
PACKAGE DIAGRAM ......................................................................................... 58
IMPORTANT NOTICE ......................................................................................... 59
REVISION HISTORY ........................................................................................... 60
2 Rev 4.5





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