BUS-INTERFACE REGISTER. CY74FCT823T Datasheet

CY74FCT823T REGISTER. Datasheet pdf. Equivalent

Part CY74FCT823T
Description 9-BIT BUS-INTERFACE REGISTER
Feature D Function, Pinout, and Drive Compatible With FCT, F Logic, and AM29823 D Reduced VOH (Typically = 3.
Manufacture etcTI
Total Page 14 Pages
Datasheet
Download CY74FCT823T Datasheet



CY74FCT823T
D Function, Pinout, and Drive Compatible
With FCT, F Logic, and AM29823
D Reduced VOH (Typically = 3.3 V) Version of
Equivalent FCT Functions
D Edge-Rate Control Circuitry for
Significantly Improved Noise
Characteristics
D Ioff Supports Partial-Power-Down Mode
Operation
D Matched Rise and Fall Times
D Fully Compatible With TTL Input and
Output Logic Levels
D ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
D 64-mA Output Sink Current
32-mA Output Source Current
D High-Speed Parallel Register With
Positive-Edge-Triggered D-Type Flip-Flops
D Buffered Common Clock-Enable (EN) and
Asynchronous-Clear (CLR) Inputs
D 3-State Outputs
CY74FCT823T
9-BIT BUS-INTERFACE REGISTER
WITH 3-STATE OUTPUTS
SCCS069A – OCTOBER 2001 – REVISED NOVEMBER 2001
P, Q, OR SO PACKAGE
(TOP VIEW)
OE
D0
D1
D2
D3
D4
D5
D6
D7
D8
CLR
GND
1
2
3
4
5
6
7
8
9
10
11
12
24 VCC
23 Y0
22 Y1
21 Y2
20 Y3
19 Y4
18 Y5
17 Y6
16 Y7
15 Y8
14 EN
13 CP
description
This bus-interface register is designed to eliminate the extra packages required to buffer existing registers and
provide extra data width for wider address/data paths or buses carrying parity. The CY74FCT823T is a
9-bit-wide buffered register with clock-enable (EN) and clear (CLR) inputs that are ideal for parity bus interfacing
in high-performance microprogrammed systems. It is ideal for use as an output port requiring high IOL/IOH.
This device is designed for high-capacitance load drive capability, while providing low-capacitance bus loading
at both inputs and outputs. Outputs are designed for low-capacitance bus loading in the high-impedance state.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2001, Texas Instruments Incorporated
1



CY74FCT823T
CY74FCT823T
9-BIT BUS-INTERFACE REGISTER
WITH 3-STATE OUTPUTS
SCCS069A OCTOBER 2001 REVISED NOVEMBER 2001
ORDERING INFORMATION
TA
PACKAGE
SPEED
(ns)
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
QSOP Q Tape and reel
6
CY74FCT823CTQCT FCT823C
SOIC SO
Tube
Tape and reel
6
6
CY74FCT823CTSOC
CY74FCT823CTSOCT
FCT823C
DIP P
40°C to 85°C
DIP P
Tube
Tube
7.5 CY74FCT823BTPC
10 CY74FCT823ATPC
CY74FCT823BTPC
CY74FCT823ATPC
QSOP Q Tape and reel
10
CY74FCT823ATQCT FCT823A
Tube
SOIC SO
Tape and reel
10
10
CY74FCT823ATSOC
CY74FCT823ATSOCT
FCT823A
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
NAME
D
CLR
CP
Y
EN
I/O
I
I
O
O
I
OE I
PIN DESCRIPTION
DESCRIPTION
D flip-flop data inputs
When CLR is low and OE is low, Q outputs are low. When CLR is high, data can be entered into the register.
Clock pulse for the register. Enters data into the register on the low-to-high clock transition.
Register 3-state outputs
Clock enable. When EN is low, data on the D input is transferred to the Q output on the low-to-high clock transition. When
EN is high, the Q outputs do not change state, regardless of the data or clock input transitions.
Output control. When OE is high, the Y outputs are in the high-impedance state. When OE is low, true register data is present
at the Y outputs.
FUNCTION TABLE
INPUTS
OE CLR EN
D
INTERNAL
OUTPUTS
FUNCTION
CP Q
Y
HHL L L Z
HH L H H Z
Z
HL XXX L Z
L LXXXL L
Clear
H H H X X NC Z
L H H X X NC NC
Hold
HHL L L Z
HH L H H Z
LHL L L L
Load
L H L H HH
H = High logic level, L = Low logic level, X = Dont care, NC = No change,
= Low-to-high transition, Z = High-impedance state
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265





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