BUS-INTERFACE REGISTER. CY74FCT825T Datasheet

CY74FCT825T REGISTER. Datasheet pdf. Equivalent

Part CY74FCT825T
Description 8-BIT BUS-INTERFACE REGISTER
Feature D Function, Pinout, and Drive Compatible With FCT, F Logic, and AM29825 D Reduced VOH (Typically = 3.
Manufacture etcTI
Datasheet
Download CY74FCT825T Datasheet



CY74FCT825T
D Function, Pinout, and Drive Compatible
With FCT, F Logic, and AM29825
D Reduced VOH (Typically = 3.3 V) Version of
Equivalent FCT Functions
D Edge-Rate Control Circuitry for
Significantly Improved Noise
Characteristics
D Ioff Supports Partial-Power-Down Mode
Operation
D Matched Rise and Fall Times
D Fully Compatible With TTL Input and
Output Logic Levels
D ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
D 64-mA Output Sink Current
32-mA Output Source Current
D High-Speed Parallel Register With
Positive-Edge-Triggered D-Type Flip-Flops
D Buffered Common Clock-Enable (EN) and
Asynchronous-Clear (CLR) Inputs
D 3-State Outputs
CY74FCT825T
8-BIT BUS-INTERFACE REGISTER
WITH 3-STATE OUTPUTS
SCCS070A – OCTOBER 2001 – REVISED NOVEMBER 2001
Q PACKAGE
(TOP VIEW)
OE1
OE2
D0
D1
D2
D3
D4
D5
D6
D7
CLR
GND
1
2
3
4
5
6
7
8
9
10
11
12
24 VCC
23 OE3
22 Y0
21 Y1
20 Y2
19 Y3
18 Y4
17 Y5
16 Y6
15 Y7
14 EN
13 CP
description
This bus-interface register is designed to eliminate the extra packages required to buffer existing registers and
provide extra data width for wider address/data paths or buses carrying parity. The CY74FCT825T is an 8-bit
buffered register with all the CY74FCT823T controls, plus multiple enables (OE1, OE2, OE3) to allow multiuser
control of the interface, e.g., CS, DMA, and RD/WR. This device is ideal for use as an output port requiring high
IOL/IOH.
This device is designed for high-capacitance load drive capability, while providing low-capacitance bus loading
at both inputs and outputs. Outputs are designed for low-capacitance bus loading in the high-impedance state.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
PACKAGE†
SPEED
(ns)
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
–40°C to 85°C QSOP – Q Tape and reel
6
CY74FCT825CTQCT FCT825C
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2001, Texas Instruments Incorporated
1



CY74FCT825T
CY74FCT825T
8-BIT BUS-INTERFACE REGISTER
WITH 3-STATE OUTPUTS
SCCS070A OCTOBER 2001 REVISED NOVEMBER 2001
NAME
D
CLR
CP
Y
EN
I/O
I
I
O
O
I
OE I
PIN DESCRIPTION
DESCRIPTION
D flip-flop data inputs
When CLR is low and OE is low, Q outputs are low. When CLR is high, data can be entered into the register.
Clock pulse for the register. Enters data into the register on the low-to-high clock transition.
Register 3-state outputs
Clock enable. When EN is low, data on the D input is transferred to the Q output on the low-to-high clock transition. When
EN is high, the Q outputs do not change state, regardless of the data or clock input transitions.
Output control. When OE is high, the Y outputs are in the high-impedance state. When OE is low, true register data is present
at the Y outputs.
FUNCTION TABLE
INPUTS
OE CLR EN
D
INTERNAL
OUTPUTS
FUNCTION
CP Q
Y
HHL L L Z
HH L H H Z
Z
HL XXX L Z
L LXXXL L
Clear
H H H X X NC Z
L H H X X NC NC
Hold
HHL L L Z
HH L H H Z
LHL L L L
Load
L H L H HH
H = High logic level, L = Low logic level, X = Dont care, NC = No change,
= Low-to-high transition, Z = High-impedance state
logic diagram (positive logic)
OE1
OE2
OE3
1
2
23
11
CLR
13
CP
14
EN
3
D0
CL
CP Q
D
22 Y0
To Seven Other Channels
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265





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