8-BIT LATCH. CY74FCT2573T Datasheet

CY74FCT2573T LATCH. Datasheet pdf. Equivalent

Part CY74FCT2573T
Description 8-BIT LATCH
Feature D Function and Pinout Compatible With the Fastest Bipolar Logic D 25-Ω Output Series Resistors Reduc.
Manufacture etcTI
Datasheet
Download CY74FCT2573T Datasheet



CY74FCT2573T
D Function and Pinout Compatible With the
Fastest Bipolar Logic
D 25-Output Series Resistors Reduce
Transmission-Line Reflection Noise
D Reduced VOH (Typically = 3.3 V) Version of
Equivalent FCT Functions
D Edge-Rate Control Circuitry for
Significantly Improved Noise
Characteristics
D Ioff Supports Partial-Power-Down Mode
Operation
D Matched Rise and Fall Times
D 3-State Outputs
D ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
D Fully Compatible With TTL Input and
Output Logic Levels
D 12-mA Output Sink Current
15-mA Output Source Current
CY74FCT2573T
8-BIT LATCH
WITH 3-STATE OUTPUTS
SCCS075 – OCTOBER 2001
Q OR SO PACKAGE
(TOP VIEW)
OE
D0
D1
D2
D3
D4
D5
D6
D7
GND
1
2
3
4
5
6
7
8
9
10
20 VCC
19 O0
18 O1
17 O2
16 O3
15 O4
14 O5
13 O6
12 O7
11 LE
description
The CY74FCT2573T is an 8-bit, high-speed CMOS, TTL-compatible buffered latch with 3-state outputs that is
ideal for driving high-capacitance loads, such as memory and address buffers. On-chip 25-termination
resistors at the outputs reduce system noise caused by reflections. The CY74FCT2573T can replace the
CY74FCT573T to reduce noise in an existing design.
When the latch-enable (LE) input is high, the flip-flops appear transparent to the data. Data that meets the
required setup times are latched when LE transitions from high to low. Data appears on the bus when the
output-enable (OE) input is low. When OE is high, the bus output is in the high-impedance state. In this mode,
data can be entered into the latches.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
PACKAGE†
SPEED
(ns)
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
QSOP – Q Tape and reel
4.7
CY74FCT2573CTQCT
FCT2573C
Tube
4.7 CY74FCT2573CTSOC
SOIC – SO
FCT2573C
Tape and reel 4.7 CY74FCT2573CTSOCT
–40°C to 85°C
QSOP – Q Tape and reel 5.2 CY74FCT2573ATQCT FCT2573A
Tube
8 CY74FCT2573TSOC
SOIC – SO
FCT2573
Tape and reel 8 CY74FCT2573TSOCT
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2001, Texas Instruments Incorporated
1



CY74FCT2573T
CY74FCT2573T
8-BIT LATCH
WITH 3-STATE OUTPUTS
SCCS075 OCTOBER 2001
logic diagram
OE 1
LE 11
D0 2
FUNCTION TABLE
INPUTS
OE LE
D
OUTPUT
O
L HH
H
LHL
L
LLX
HXX
Q0
Z
H = High logic level, L = Low logic level,
X = Dont care, Z = High-impedance
state, Q0 = Previous state of flip flops
(Q01)
CP
Q
D
19
O0
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
DC input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
DC output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
DC output current (maximum sink current/pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 mA
Package thermal impedance, θJA (see Note 1): Q package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68°C/W
SO package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
Ambient temperature range with power applied, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 135°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under absolute maximum ratingsmay cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditionsis not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 2)
MIN NOM MAX UNIT
VCC Supply voltage
VIH High-level input voltage
VIL Low-level input voltage
IOH High-level output current
IOL Low-level output current
TA Operating free-air temperature
NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation.
4.75
2
40
5 5.25 V
V
0.8 V
15 mA
12 mA
85 °C
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265





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