8-BIT REGISTERS. CY74FCT574T Datasheet

CY74FCT574T REGISTERS. Datasheet pdf. Equivalent

Part CY74FCT574T
Description 8-BIT REGISTERS
Feature D Function, Pinout, and Drive Compatible With FCT and F Logic D Reduced VOH (Typically = 3.3 V) Vers.
Manufacture etcTI
Datasheet
Download CY74FCT574T Datasheet



CY74FCT574T
D Function, Pinout, and Drive Compatible
With FCT and F Logic
D Reduced VOH (Typically = 3.3 V) Versions
of Equivalent FCT Functions
D Edge-Rate Control Circuitry for
Significantly Improved Noise
Characteristics
D Ioff Supports Partial-Power-Down Mode
Operation
D Matched Rise and Fall Times
D Fully Compatible With TTL Input and
Output Logic Levels
D ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
D Edge-Triggered D-Type Inputs
D 250-MHz Typical Switching Rate
D CY54FCT574T
– 32-mA Output Sink Current
– 12-mA Output Source Current
D CY74FCT574T
– 64-mA Output Sink Current
– 32-mA Output Source Current
D 3-State Outputs
CY54FCT574T, CY74FCT574T
8-BIT REGISTERS
WITH 3-STATE OUTPUTS
SCCS073 – OCTOBER 2001
CY54FCT574T . . . D PACKAGE
CY74FCT574T . . . Q OR SO PACKAGE
(TOP VIEW)
OE
D0
D1
D2
D3
D4
D5
D6
D7
GND
1
2
3
4
5
6
7
8
9
10
20 VCC
19 O0
18 O1
17 O2
16 O3
15 O4
14 O5
13 O6
12 O7
11 CP
CY54FCT574T . . . L PACKAGE
(TOP VIEW)
D2
3 2 1 20 19
4 18
O1
D3 5
17 O2
D4 6
16 O3
D5 7
15 O4
D6
8 14
9 10 11 12 13
O5
description
The ’FCT574T devices are high-speed, low-power, octal D-type flip-flops, featuring separate D-type inputs for
each flip-flop. These devices have 3-state outputs for bus-oriented applications. A buffered clock (CP) and
output-enable (OE) inputs are common to all flip-flops. The ’FCT574T are identical to ’FCT374T, except for a
flow-through pinout to simplify board design. The eight flip-flops in the ’FCT574T store the state of their
individual D inputs that meet the setup-time and hold-time requirements on the low-to-high CP transition. When
OE is low, the contents of the eight flip-flops are available at the outputs. When OE is high, the outputs are in
the high-impedance state. The state of OE does not affect the state of the flip-flops.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the device when it is powered down.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2001, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1



CY74FCT574T
CY54FCT574T, CY74FCT574T
8-BIT REGISTERS
WITH 3-STATE OUTPUTS
SCCS073 OCTOBER 2001
ORDERING INFORMATION
TA
PACKAGE
SPEED
(ns)
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
QSOP Q Tape and reel 5.2 CY74FCT574CTQCT
FCT574C
Tube
5.2 CY74FCT574CTSOC
SOIC SO
FCT574C
Tape and reel 5.2 CY74FCT574CTSOCT
QSOP Q Tape and reel 6.5 CY74FCT574ATQCT
FCT574A
40°C to 85°C
Tube
6.5 CY74FCT574ATSOC
SOIC SO
FCT574A
Tape and reel 6.5 CY74FCT574ATSOCT
QSOP Q Tape and reel 10 CY74FCT574TQCT
FCT574
Tube
10 CY74FCT574TSOC
SOIC SO
Tape and reel 10 CY74FCT574TSOCT
FCT574
CDIP D Tube
6.2 CY54FCT574CTDMB
55°C to 125°C CDIP D Tube
7.2 CY54FCT574ATDMB
LCC L
Tube
7.2 CY54FCT574ATLMB
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
D CP OE
OUTPUT
O
HL
H
LL
L
XXH
Z
H = High logic level, L = Low logic level,
X = Dont care, Z = High-impedance state,
= Low-to-high clock transition
logic diagram (positive logic)
1
OE
CP 11
2
D0
C1
Q
1D
19
O0
To Seven Other Channels
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265





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