8-BIT REGISTERS. CY54FCT377T Datasheet

CY54FCT377T REGISTERS. Datasheet pdf. Equivalent

Part CY54FCT377T
Description 8-BIT REGISTERS
Feature CY54FCT377T, CY74FCT377T 8-BIT REGISTERS D Function, Pinout, and Drive Compatible With FCT and F Lo.
Manufacture etcTI
Datasheet
Download CY54FCT377T Datasheet



CY54FCT377T
CY54FCT377T, CY74FCT377T
8-BIT REGISTERS
D Function, Pinout, and Drive Compatible
With FCT and F Logic
D Reduced VOH (Typically = 3.3 V) Versions of
Equivalent FCT Functions
D Edge-Rate Control Circuitry for
Significantly Improved Noise
Characteristics
D Ioff Supports Partial-Power-Down Mode
Operation
D Matched Rise and Fall Times
D ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
D Fully Compatible With TTL Input and
Output Logic Levels
D Clock Enable for Address and Data
Synchronization Application
D Eight Edge-Triggered D-Type Flip-Flops
D CY54FCT377T
– 32-mA Output Sink Current
– 12-mA Output Source Current
D CY74FCT377T
– 64-mA Output Sink Current
– 32-mA Output Source Current
SCCS023A – MAY 1994 – REVISED OCTOBER 2001
SN74FCT377T . . . Q OR SO PACKAGE
(TOP VIEW)
CE
O0
D0
D1
O1
O2
D2
D3
O3
GND
1
2
3
4
5
6
7
8
9
10
20 VCC
19 O7
18 D7
17 D6
16 O6
15 O5
14 D5
13 D4
12 O4
11 CP
SN54FCT377T . . . L PACKAGE
(TOP VIEW)
3 2 1 20 19
D1 4
18 D7
O1 5
17 D6
O2 6
16 O6
D2 7
15 O5
D3
8 14
9 10 11 12 13
D5
description
The ’FCT377T devices have eight triggered D-type flip-flops with individual data (D) inputs. The common
buffered clock (CP) inputs load all flip-flops simultaneously when the clock-enable (CE) input is low. The register
is fully edge triggered. The state of each D input at one setup time before the low-to-high clock transition is
transferred to the corresponding flip-flop output (O). CE must be stable only one setup time prior to the
low-to-high clock transition for predictable operation.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the device when it is powered down.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2001, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1



CY54FCT377T
CY54FCT377T, CY74FCT377T
8-BIT REGISTERS
SCCS023A MAY 1994 REVISED OCTOBER 2001
ORDERING INFORMATION
TA
PACKAGE
SPEED
(ns)
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
QSOP Q Tape and reel
5.2 CY74FCT377CTQCT FCT377C
Tube
SOIC SO
Tape and reel
5.2 CY74FCT377CTSOC
FCT377C
5.2 CY74FCT377CTSOCT
40°C to 85°C QSOP Q Tape and reel
7.2 CY74FCT377ATQCT FCT377A
Tube
SOIC SO
Tape and reel
7.2 CY74FCT377ATSOC
FCT377A
7.2 CY74FCT377ATSOCT
QSOP Q Tape and reel
13 CY74FCT377TQCT
FCT377
55°C to 125°C LCC L
Tube
Tube
5.5 CY54FCT377CTLMB
8.3 CY54FCT377ATLMB
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
CP CE
D
OUTPUT
O
OPERATING
MODE
l
l
h
XH
hH
lL
X
X No change
Load 1
Load 0
Hold
H = High logic level, h = High logic level one setup time prior
to the low-to-high clock transition, L = Low logic level,
l = Low logic level one setup time prior to the low-to-high
clock transition, X = Dont care, = Low-to-high clock
transition
logic diagram
CP 11
CE 1
3
D0
CP
Q
D
2
O0
To Seven Other Channels
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265





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