Ultralow-Power ADC. ADS4229 Datasheet

ADS4229 ADC. Datasheet pdf. Equivalent

Part ADS4229
Description Ultralow-Power ADC
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ADS4229
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ADS4229
SBAS550C – JUNE 2011 – REVISED MAY 2015
ADS4229 Dual-Channel, 12-Bit, 250-MSPS Ultralow-Power ADC
1 Features
1 Maximum Sample Rate: 250 MSPS
• Ultralow Power with Single 1.8-V Supply:
– 545-mW Total Power at 250 MSPS
• High Dynamic Performance:
– 80.8-dBc SFDR at 170 MHz
– 69.4-dBFS SNR at 170 MHz
• Crosstalk: > 90 dB at 185 MHz
• Programmable Gain Up to 6 dB for
SNR and SFDR Trade-off
• DC Offset Correction
• Output Interface Options:
– 1.8-V Parallel CMOS Interface
– DDR LVDS With Programmable Swing:
– Standard Swing: 350 mV
– Low Swing: 200 mV
• Supports Low Input Clock Amplitude
Down to 200 mVPP
• Package: 9-mm × 9-mm, 64-Pin Quad Flat
No-Lead (QFN) Package
3 Description
The ADS4229 is a member of the ADS42xx ultralow-
power family of dual-channel, 12-bit and 14-bit
analog-to-digital converters (ADCs). Innovative
design techniques are used to achieve high dynamic
performance, while consuming extremely low power
with a 1.8-V supply. This topology makes the
ADS4229 well-suited for multi-carrier, wide-bandwidth
communications applications.
The ADS4229 has gain options that can be used to
improve spurious-free dynamic range (SFDR)
performance at lower full-scale input ranges. This
device also includes a dc offset correction loop that
can be used to cancel the ADC offset. Both double
data rate (DDR) low-voltage differential signaling
(LVDS) and parallel complementary metal oxide
semiconductor (CMOS) digital output interfaces are
available in a compact QFN-64 PowerPAD™
package.
The device includes internal references while the
traditional reference pins and associated decoupling
capacitors have been eliminated. The ADS4229 is
specified over the industrial temperature range
(–40°C to +85°C).
2 Applications
• Wireless Communications Infrastructure
• Software Defined Radio
• Power Amplifier Linearization
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
ADS4229
VQFN (64)
9.00 mm × 9.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
ADS4229
ADS4229 Block Diagram
INP_A
INM_A
CLKP
CLKM
INP_B
INM_B
Sampling
Circuit
Sampling
Circuit
12-bit ADC
CLK
Gen
12-bit ADC
LVDS
DA0P
DA0M
DA12P
DA12M
CLKOUTP
CLKOUTM
DB0P
DB0M
DB12P
DB12M
VCM Reference
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.



ADS4229
ADS4229
SBAS550C – JUNE 2011 – REVISED MAY 2015
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Device Comparison Table..................................... 4
6 Pin Configuration and Functions ......................... 5
7 Specifications......................................................... 9
7.1 Absolute Maximum Ratings ...................................... 9
7.2 ESD Ratings.............................................................. 9
7.3 Recommended Operating Conditions....................... 9
7.4 Thermal Information ................................................ 10
7.5 Electrical Characteristics: ADS4229 (250 MSPS)... 10
7.6 Electrical Characteristics: General .......................... 12
7.7 Digital Characteristics ............................................. 13
7.8 LVDS and CMOS Modes Timing Requirements..... 14
7.9 LVDS Timings at Lower Sampling Frequencies ..... 15
7.10 CMOS Timings at Lower Sampling Frequencies .. 15
7.11 Serial Interface Timing Characteristics ................. 17
7.12 Reset Timing (Only when Serial Interface is
Used)........................................................................ 18
7.13 Typical Characteristics .......................................... 19
8 Detailed Description ............................................ 26
8.1 Overview ................................................................. 26
8.2 Functional Block Diagram ....................................... 26
8.3 Feature Description................................................. 27
8.4 Device Functional Modes........................................ 29
8.5 Programming........................................................... 33
8.6 Register Maps ......................................................... 37
9 Application and Implementation ........................ 47
9.1 Application Information............................................ 47
9.2 Typical Application ................................................. 53
10 Power Supply Recommendations ..................... 55
10.1 Sharing DRVDD and AVDD Supplies ................... 55
10.2 Using DC/DC Power Supplies .............................. 55
10.3 Power Supply Bypassing ...................................... 55
11 Layout................................................................... 55
11.1 Layout Guidelines ................................................. 55
11.2 Layout Example .................................................... 56
12 Device and Documentation Support ................. 57
12.1 Device Support...................................................... 57
12.2 Documentation Support ........................................ 58
12.3 Community Resources.......................................... 59
12.4 Trademarks ........................................................... 59
12.5 Electrostatic Discharge Caution ............................ 59
12.6 Glossary ................................................................ 59
13 Mechanical, Packaging, and Orderable
Information ........................................................... 59
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (August 2012) to Revision C
Page
• Added Pin Configuration and Functions section, ESD Rating table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
Changes from Revision A (October 2011) to Revision B
Page
• Changed first sub-bullet of High Dynamic Performance Features bullet ............................................................................... 1
• Changed footnote 1 in CMOS Timings at Lower Sampling Frequencies............................................................................. 15
• Changed row D5 and consolidated the two DB rows in Table 10........................................................................................ 37
• Changed Register Address D5h........................................................................................................................................... 46
• Changed title of Register Address DBh, consolidated two DBh registers into one.............................................................. 46
Changes from Original (June 2011) to Revision A
Page
• Changed ADS4229 Input Common-Mode Voltage parameter in Table 1 .............................................................................. 4
• Changed AC power-supply rejection ratio parameter test condition in ADS4229 Electrical Characteristics table .............. 11
• Updated Figure 3.................................................................................................................................................................. 16
• Updated Figure 25................................................................................................................................................................ 22
• Updated Figure 31................................................................................................................................................................ 23
• Updated Figure 32................................................................................................................................................................ 23
• Changed Time Constant, TCCLK × 1/fS (ms) column and footnote 1 in Table 3 ................................................................... 28
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