POWER AMPLIFIER. TPA3123D2 Datasheet

TPA3123D2 AMPLIFIER. Datasheet pdf. Equivalent

TPA3123D2 Datasheet
Recommendation TPA3123D2 Datasheet
Part TPA3123D2
Description 25-W STEREO CLASS-D AUDIO POWER AMPLIFIER
Feature TPA3123D2; www.ti.com TPA3123D2 SLOS541C – JULY 2007 – REVISED AUGUST 2010 25-W STEREO CLASS-D AUDIO POWER AMP.
Manufacture etcTI
Datasheet
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Texas Instruments TPA3123D2
www.ti.com
TPA3123D2
SLOS541C – JULY 2007 – REVISED AUGUST 2010
25-W STEREO CLASS-D AUDIO POWER AMPLIFIER
Check for Samples: TPA3123D2
FEATURES
1
2 25-W/ch into a 4-Load from a 27-V Supply
• 20-W/ch into a 4-Load from a 24-V Supply
• Operates from 10 V to 30 V
• Efficient Class-D Operation Eliminates Need
for Heat Sinks
• Four Selectable, Fixed-Gain Settings
• Internal Oscillator (No External Components
Required)
• Single-Ended Analog Inputs
• Thermal and Short-Circuit Protection With
Auto Recovery
• Space-Saving Surface-Mount 24-Pin TSSOP
Package
TPA3120D2
• Pin-to-Pin compatible with TPA3120D2
• Advanced Power-Off Pop Reduction
APPLICATIONS
• Televisions
DESCRIPTION
The TPA3123D2 is a 25-W (per channel) efficient,
Class-D audio power amplifier for driving stereo
speakers in a single-ended configuration or a mono
speaker in a bridge-tied-load configuration. The
TPA3123D2 can drive stereo speakers as low as 4 .
The efficiency of the TPA3123D2 eliminates the need
for an external heat sink when playing music.
The gain of the amplifier is controlled by two gain
select pins. The gain selections are 20, 26, 32,
36 dB.
The patented start-up and shut-down sequences
minimize pop noise in the speakers without additional
circuitry.
Left Channel
Right Channel
SIMPLIFIED APPLICATION CIRCUIT
1 mF
1 mF
1 mF
TPA3123D2
0.22 mF
LIN
BSR
22 mH 470 mF
RIN ROUT
PGNDR
0.68 mF
PGNDL
0.68 mF
BYPASS
AGND
LOUT
BSL
22 mH
0.22 mF
470 mF
10 V to 30 V
Shutdown
Control
Mute Control
AVCC
SD
MUTE
PVCCL
PVCCR
VCLAMP
1 mF
GAIN0
GAIN1
10 V to 30 V
} 4-Step Gain
Control
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
System Two, Audio Precision are trademarks of Audio Precision, Inc.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2010, Texas Instruments Incorporated



Texas Instruments TPA3123D2
TPA3123D2
SLOS541C – JULY 2007 – REVISED AUGUST 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
PWP (TSSOP) PACKAGE
(TOP VIEW)
PVCCL
SD
PVCCL
MUTE
LIN
RIN
BYPASS
AGND
AGND
PVCCR
VCLAMP
PVCCR
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
PGNDL
PGNDL
LOUT
BSL
AVCC
AVCC
GAIN0
GAIN1
BSR
ROUT
PGNDR
PGNDR
PIN
NAME
SD
RIN
LIN
GAIN0
GAIN1
MUTE
BSL
PVCCL
LOUT
PGNDL
VCLAMP
BSR
ROUT
PGNDR
PVCCR
AGND
AGND
BYPASS
AVCC
Thermal pad
24-PIN
(PWP)
2
6
5
18
17
4
21
1, 3
22
23, 24
11
16
15
13, 14
10, 12
9
8
7
19, 20
Die pad
Table 1. PIN FUNCTIONS
I/O/P
DESCRIPTION
I
Shutdown signal for IC (low = disabled, high = operational). TTL logic levels with compliance to
AVCC
I Audio input for right channel
I Audio input for left channel
I Gain select least-significant bit. TTL logic levels with compliance to AVCC
I Gain select most-significant bit. TTL logic levels with compliance to AVCC
I
Mute signal for quick disable/enable of outputs (high = outputs switch at 50% duty cycle, low =
outputs enabled). TTL logic levels with compliance to AVCC
I/O Bootstrap I/O for left channel
P Power supply for left-channel H-bridge, not internally connected to PVCCR or AVCC
O Class-D 1/2-H-bridge positive output for left channel
P Power ground for left-channel H-bridge
P Internally generated voltage supply for bootstrap capacitors
I/O Bootstrap I/O for right channel
O Class-D 1/2-H-bridge negative output for right channel
P Power ground for right-channel H-bridge.
P Power supply for right-channel H-bridge, not connected to PVCCL or AVCC
P Analog ground for digital/analog cells in core
P Analog ground for analog cells in core
O
Reference for preamplifier inputs. Nominally equal to AVCC/8. Also controls start-up time via
external capacitor sizing.
P High-voltage analog power supply. Not internally connected to PVCCR or PVCCL
P
Connect to ground. Thermal pad should be soldered down on all applications to secure the
device properly to the printed wiring board.
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Copyright © 2007–2010, Texas Instruments Incorporated
Product Folder Link(s) :TPA3123D2



Texas Instruments TPA3123D2
www.ti.com
TPA3123D2
SLOS541C – JULY 2007 – REVISED AUGUST 2010
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
VCC
VI
VIN
TA
TJ
Tstg
RL
ESD
Supply voltage
Logic input voltage
Analog input voltage
Continuous total power dissipation
Operating free-air temperature range
Operating junction temperature range
Storage temperature range
Load resistance (minimum value)
Electrostatic Discharge
AVCC, PVCC
SD, MUTE, GAIN0, GAIN1
RIN, LIN
Human-body model (all pins)
Charged-device model (all pins)
VALUE
UNIT
–0.3 to 36
V
–0.3 to VCC + 0.3
–0.3 to 7
V
V
See the Thermal Information table
–40 to 85
°C
–40 to 150
°C
–65 to 150
°C
3.2
± 2 kV
± 500
V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operations of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION
THERMAL METRIC(1)(2)
TPA3123D2
PWP
UNITS
24 PINS
qJA
qJCtop
qJB
yJT
yJB
qJCbot
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
30.2
27.8
6.8
°C/W
0.3
32.1
0.5
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
RECOMMENDED OPERATING CONDITIONS
VCC Supply voltage
VIH High-level input voltage
VIL Low-level input voltage
IIH High-level input current
IIL Low-level input current
TA Operating free-air temperature
PVCC, AVCC
SD, MUTE, GAIN0, GAIN1
SD, MUTE, GAIN0, GAIN1
SD, VI = VCC, VCC = 30 V
MUTE, VI = VCC, VCC = 30 V
GAIN0, GAIN1, VI = VCC, VCC = 24 V
SD, VI = 0, VCC = 30 V
MUTE, VI = 0 V, VCC = 30 V
GAIN0, GAIN1, VI = 0 V, VCC = 24 V
MIN MAX UNIT
10 30 V
2V
0.8 V
125
125 mA
125
1
1 mA
1
–40 85 °C
Copyright © 2007–2010, Texas Instruments Incorporated
Product Folder Link(s) :TPA3123D2
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