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Analog Front-End. AFE032 Datasheet

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Analog Front-End. AFE032 Datasheet






AFE032 Front-End. Datasheet pdf. Equivalent




AFE032 Front-End. Datasheet pdf. Equivalent





Part

AFE032

Description

Power-Line Communications Analog Front-End



Feature


AFE032 www.ti.com SBOS669A – AUGUST 2013 – REVISED DECEMBER 2013 Power-Li ne Communications Analog Front-End Chec k for Samples: AFE032 FEATURES 1 •23 45 Supports: – CENELEC Bands A, B, C, D – ARIB STD-T84, FCC – FSK, SFSK, and NB-OFDM • Conforms To: – EN500 65-1, -2, -3, -7 – FCC, Part 15 – A RIB STD-T84 • Standards: – G3, PRIM E, P1901.2, ITU-G.hnem • Programmable Tx L.
Manufacture

Texas Instruments

Datasheet
Download AFE032 Datasheet


Texas Instruments AFE032

AFE032; ow-Pass Filters and Rx Band-Pass Filters • Integrated Power-Line Driver with Thermal and Overcurrent Protection • Low-Power Consumption: – 50 mW (Recei ver Mode) • Receive Sensitivity: 10 VRMS (Typ) • Four-Wire SPI™ Interf ace • Three Integrated Zero-Crossing Detectors • Package: QFN-48 PowerPAD • Extended Temperature Range: –4 0°C to +125°C PA_NRF TX_RX_NRF DAC_NRF .


Texas Instruments AFE032

The integrated receiver is able to detec t signals down to 10 μVRMS (G3-FCC mod e) and is capable of a wide range of ga in options to adapt to varying input-si gnal conditions. The monolithic integra ted circuit provides high reliability i n demanding power-line communication ap plications. The AFE032 transmit power a mplifier operates from a single supply in the range of 7 V.


Texas Instruments AFE032

to 24 V. At typical load current (IOUT = 1.5 APEAK), a wide output swing provi des a 12-VPP capability with a nominal 15-V supply. The device is internally p rotected against overtemperature and sh ort-circuit conditions. The device also provides a selectable current limit. A n interrupt output is provided, indicat ing current limit, thermal limit, and u ndervoltage. A shu.

Part

AFE032

Description

Power-Line Communications Analog Front-End



Feature


AFE032 www.ti.com SBOS669A – AUGUST 2013 – REVISED DECEMBER 2013 Power-Li ne Communications Analog Front-End Chec k for Samples: AFE032 FEATURES 1 •23 45 Supports: – CENELEC Bands A, B, C, D – ARIB STD-T84, FCC – FSK, SFSK, and NB-OFDM • Conforms To: – EN500 65-1, -2, -3, -7 – FCC, Part 15 – A RIB STD-T84 • Standards: – G3, PRIM E, P1901.2, ITU-G.hnem • Programmable Tx L.
Manufacture

Texas Instruments

Datasheet
Download AFE032 Datasheet




 AFE032
AFE032
www.ti.com
SBOS669A – AUGUST 2013 – REVISED DECEMBER 2013
Power-Line Communications Analog Front-End
Check for Samples: AFE032
FEATURES
1
2345 Supports:
– CENELEC Bands A, B, C, D
– ARIB STD-T84, FCC
– FSK, SFSK, and NB-OFDM
• Conforms To:
– EN50065-1, -2, -3, -7
– FCC, Part 15
– ARIB STD-T84
• Standards:
– G3, PRIME, P1901.2, ITU-G.hnem
• Programmable Tx Low-Pass Filters and
Rx Band-Pass Filters
• Integrated Power-Line Driver with Thermal and
Overcurrent Protection
• Low-Power Consumption:
– 50 mW (Receiver Mode)
• Receive Sensitivity: 10 μVRMS (Typ)
• Four-Wire SPI™ Interface
• Three Integrated Zero-Crossing Detectors
• Package: QFN-48 PowerPAD™
• Extended Temperature Range:
–40°C to +125°C
The integrated receiver is able to detect signals down
to 10 μVRMS (G3-FCC mode) and is capable of a wide
range of gain options to adapt to varying input-signal
conditions. The monolithic integrated circuit provides
high reliability in demanding power-line
communication applications.
The AFE032 transmit power amplifier operates from a
single supply in the range of 7 V to 24 V. At typical
load current (IOUT = 1.5 APEAK), a wide output swing
provides a 12-VPP capability with a nominal 15-V
supply.
The device is internally protected against
overtemperature and short-circuit conditions. The
device also provides a selectable current limit. An
interrupt output is provided, indicating current limit,
thermal limit, and undervoltage. A shutdown pin is
also available, and can be used to quickly place the
device into the lowest-power state. Each functional
block can be enabled or disabled to optimize power
dissipation through the serial peripheral interface
(SPI),
The AFE032 is housed in a thermally-enhanced,
surface-mount, PowerPAD, QFN-48 package.
Operation is specified over the extended industrial
junction temperature range of –40°C to +125°C.
PA_IN
PA_VS PA_ISET
PA_OUT ZC_IN3 ZC_IN2 ZC_IN1
APPLICATIONS
DVDD
DGND
• eMetering
• Home Area Networks
AVDD1
AVDD2
AGND1
AGND2
Bias
and
References
Power
Amplifier
• Lighting
• Solar
• Pilot Wires and EVSEs
SCLK
DIN
DOUT
CS
DAC
Digital Interface
(SPI)
AFE032
DESCRIPTION
SD
RX_FLAG
TX_FLAG
Control Registers
DAC
TX PGA
The AFE032 is a low-cost, integrated, power-line
communications (PLC), analog front-end (AFE)
device capable of transformer-coupled connections to
the power-line while under the control of a digital
signal processor (DSP) or microcontroller. This
device is ideal for driving high-current, low-impedance
lines up to 1.9 A into reactive loads.
INT
XCLK
DAC_OUT TX_PGA_IN
ZC1
ZC2
ZC3
RX PGA2
Programmable
Filter
RX PGA1
ZC_OUT1
ZC_OUT2
ZC_OUT3
PA_GND
TSENSE
RX_PGA2_IN
RX_PGA2_OUT
RX_F_OUT
RX_PGA1_IN TX_F_OUT
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
2
Illinois Capacitor is a trademark of Illinois Capacitor, Inc.
3
SPI is a trademark of Motorola Inc.
4
All other trademarks are the property of their respective owners.
5
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated




 AFE032
AFE032
SBOS669A – AUGUST 2013 – REVISED DECEMBER 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range, unless otherwise noted.
PA_VS
AVDD
DVDD
TA
Tstg
TJ
ESD
Supply voltage (pins 44, 45)
Pins 3, 4, 6, 7, 8, 10
Voltage (2)
Pins 13, 21, 28, 31, 32, 38, 39
Pins 18, 19
Signal input terminals
Pin 27
Pins 3, 4, 6, 7, 8, 10
Current (2)
Pins 13, 21, 28, 31, 32, 38, 39
Pins 18, 19
Pin 35
Pins 5, 9, 47, 48
Voltage
Pins 14, 17, 20, 22, 33, 36, 37
Signal output terminals
Pins 42, 43
Current; short-circuit to GND Pins 5, 9, 47, 48
Current; short-circuit to GND Pins 14, 17, 20, 22, 33, 36, 37
Current; short-circuit to GND Pins 42, 43
Analog supply voltage (pins 11, 30)
Digital supply voltage
Operating temperature(3)
Storage temperature
Junction temperature
Electrostatic discharge
ratings
Human body model (HBM)
Machine model (MM)
Charged device model (CDM)
VALUE
+26
DGND – 0.4 to DVDD + 0.4
AGND – 0.4 to AVDD + 0.4
PA_GND – 0.4 to PA_VS + 0.4
AVDD + 0.4 to 26
±10
±10
±10
±10
DGND – 0.4 to DVDD + 0.4
AGND – 0.4 to AVDD + 0.4
PA_GND – 0.4 to PA_VS + 0.4
Continuous
Continuous
Continuous
5.5
5.5
–40 to +150
–55 to +150
+150
3000
200
500
UNIT
V
V
V
V
V
mA
mA
mA
mA
V
V
V
V
V
°C
°C
°C
V
V
V
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and do not imply functional operation of the device at these or any other conditions beyond those indicated. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
(2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.4 V beyond the supply rails should
be current limited to 10 mA or less.
(3) The device automatically goes to shutdown above +165°C.
THERMAL INFORMATION
θJA
θJCtop
θJB
ψJT
ψJB
θJCbot
THERMAL METRIC(1)
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
AFE032
RGZ (QFN)
48 PINS
22.5
12.1
7.5
2.0
5.4
1.7
UNITS
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
2 Submit Documentation Feedback
Product Folder Links: AFE032
Copyright © 2013, Texas Instruments Incorporated




 AFE032
AFE032
www.ti.com
SBOS669A – AUGUST 2013 – REVISED DECEMBER 2013
ELECTRICAL CHARACTERISTICS: Transmitter
At TCASE = +25°C, VPAVS = 15 V, and VAVDD = VDVDD = 3.3 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
DAC
Resolution
DR Data rate(1)
12-bit DAC, internal VREF = 0.7 V
DAC pin high, 12-bit word
GE Gain error
DAC OUTPUT
Full-scale range, TJ = –40°C to +125°C
RO Output resistance
TX_PGA INPUT
G = 1, f = 100 kHz
Input voltage range
RI Input resistance
G Gain
GE Gain error
Gain error drift
TX_PGA FREQUENCY RESPONSE
BW Bandwidth(3)
TX PATH TRANSMITTER NOISE(4)
CEN-A
CEN-B
Integrated noise
at PA output(5)
CEN-C
CEN-D
ARIB STD-T84
FCC-LOW
G3-FCC
POWER AMPLIFIER (PA) INPUT
G = 1.15 V/V
G = 2.3 V/V
G = 3.25 V/V
G = 4.6 V/V
Includes DAC, programmable filter,
and TX_PGA for all gains, TJ = –40°C to +125°C
Includes DAC, programmable filter,
and TX_PGA for all gains, TJ = –40°C to +125°C
CL = 20 pF, G = 1.15 V/V,
TJ = –40°C to +125°C
CL = 20 pF, G = 2.3 V/V,
TJ = –40°C to +125°C
CL = 20 pF, G = 3.25 V/V,
TJ = –40°C to +125°C
CL = 20 pF, G = 4.6 V/V,
TJ = –40°C to +125°C
35 kHz to 95 kHz
95 kHz to 125 kHz
125 kHz to 140 kHz
140 kHz to 148 kHz
35 kHz to 420 kHz
35 kHz to 125 kHz
150 kHz to 490 kHz
Input voltage range
For linear operation
Input impedance
PA FREQUENCY RESPONSE
BW Bandwidth
SR Slew rate
Full-power bandwidth
PSRR
Power-supply rejection ratio
ILOAD = 0 mA
PA_VS = 24 V, 20-V step
PA_VS = 24 V, VOUT = 20 VPP
RTI, dc to f = 50 kHz
MIN
TYP
MAX UNIT
165
–2%
171
4.8
±0.5%
176 µV
5.2 MSPS
2%
1 kΩ
(AGND +
0.15) /
gain
(AVDD – 0.15) /
gain
52
34
26
20
1.15, 2.3, 3.25, 4.6(2)
–2%
±0.1%
2%
V
kΩ
kΩ
kΩ
kΩ
V/V
–10 ±3 +10 ppm/°C
(PA_GND
+ 0.4) /
gain
3.4
80
30
21.5
17.5
15.5
MHz
MHz
MHz
MHz
370 µVRMS
220 µVRMS
160 µVRMS
98 µVRMS
640 µVRMS
384 µVRMS
565 µVRMS
(PA_VS – 0.4) /
gain
17
V
kΩ
3.82
75
1
94
4.23
MHz
V/µs
MHz
dB
(1) Refer to the Application Information section.
(2) This parameter is from DAC_OUT to TX_F_OUT. This parameter includes the LPF gain error and is the dc gain. Adding LPF causes
some loss of gain flatness.
(3) This parameter is internal to the device. Bandwidth is designed and simulated over corners to ensure a low-distortion PGA in the
application.
(4) Includes the DAC, programmable filter, TX_PGA, and PA noise-reducing capacitor = 1 nF from DAC_NRF to ground, PA_NRF to
ground, and TX_RF_NRF to ground.
(5) Includes the DAC, TX_PGA (gain = 4.6), LPF, and PA.
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: AFE032
Submit Documentation Feedback
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