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Clock Buffer. 5PB1204 Datasheet

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Clock Buffer. 5PB1204 Datasheet






5PB1204 Buffer. Datasheet pdf. Equivalent




5PB1204 Buffer. Datasheet pdf. Equivalent





Part

5PB1204

Description

TCXO/LVCMOS Clock Buffer



Feature


3-Channel High-Performance TCXO/LVCMOS C lock Buffer Family 5PB12xx Datasheet Description The 5PB12xx is a high-perfo rmance TCXO/LVCMOS clock fanout buffer family with individual OE pin for each output. The CLKIN pin can accept either a square wave (LVCMOS) or clipped sine wave (such as TCXO clipped sine wave o utput) as input. There are 3 different fan-out versions a.
Manufacture

Renesas

Datasheet
Download 5PB1204 Datasheet


Renesas 5PB1204

5PB1204; vailable: 1:3, 1:4 and 1:6. The 5PB12xx has industry-leading low jitter and ext remely low current consumption, making it ideal for smart mobile devices. Typi cal Applications • Smart Mobile Hands ets • RF and baseband peripheral cloc k distribution • Automotive Features • Extremely low operating and standb y current consumption • Low RMS addit ive phase jitter • Family su.


Renesas 5PB1204

pports 1.8V to 3.3V power supply voltage : • For 1.8V supply: 5PB1203, 5PB1204 , 5PB1206 • For 2.5V / 3.3V supply: 5 PB1213, 5PB1214, 5PB1216 • Three, fou r, and six outputs with individual Outp ut Enable pin • One input • OE_OSC control pin to enable/disable reference TCXO/XO • Small 10-pin, 16-pin and 2 0-pin packages available • Industrial -40º to +105ºC temperature rang.


Renesas 5PB1204

e Block Diagram CLKIN OE_OSC OE1 OE2 O E6 Control Logic CLKOUT1 CLKOUT2 CLKO UT6 ©2020 Renesas Electronics Corpora tion 1 Pin Assignments 5PB12xx Datas heet OE1 CLKIN GND CLKOUT1 CLKIN OE1 G ND CLKOUT1 CLKOUT2 GND VDD CLKIN E_OSC OE3 1 2 3 4 5 10 CLKOUT3 9 CLKOUT2 8 CLKOUT1 7 OE2 6 OE1 5PB1203 / 5PB1213 10-pin 2mm x 2mm DFN 16 15 1 4 13 O E2 1 12 VDD   20 1.

Part

5PB1204

Description

TCXO/LVCMOS Clock Buffer



Feature


3-Channel High-Performance TCXO/LVCMOS C lock Buffer Family 5PB12xx Datasheet Description The 5PB12xx is a high-perfo rmance TCXO/LVCMOS clock fanout buffer family with individual OE pin for each output. The CLKIN pin can accept either a square wave (LVCMOS) or clipped sine wave (such as TCXO clipped sine wave o utput) as input. There are 3 different fan-out versions a.
Manufacture

Renesas

Datasheet
Download 5PB1204 Datasheet




 5PB1204
3-Channel High-Performance
TCXO/LVCMOS Clock Buffer Family
5PB12xx
Datasheet
Description
The 5PB12xx is a high-performance TCXO/LVCMOS clock
fanout buffer family with individual OE pin for each output.
The CLKIN pin can accept either a square wave (LVCMOS)
or clipped sine wave (such as TCXO clipped sine wave
output) as input.
There are 3 different fan-out versions available: 1:3, 1:4
and 1:6.
The 5PB12xx has industry-leading low jitter and extremely
low current consumption, making it ideal for smart mobile
devices.
Typical Applications
Smart Mobile Handsets
RF and baseband peripheral clock distribution
Automotive
Features
Extremely low operating and standby current
consumption
Low RMS additive phase jitter
Family supports 1.8V to 3.3V power supply voltage:
For 1.8V supply: 5PB1203, 5PB1204, 5PB1206
For 2.5V / 3.3V supply: 5PB1213, 5PB1214, 5PB1216
Three, four, and six outputs with individual Output Enable
pin
One input
OE_OSC control pin to enable/disable reference
TCXO/XO
Small 10-pin, 16-pin and 20-pin packages available
Industrial -40º to +105ºC temperature range
Block Diagram
CLKIN
OE_OSC
OE1
OE2
OE6
Control
Logic
CLKOUT1
CLKOUT2
CLKOUT6
©2020 Renesas Electronics Corporation
1




 5PB1204
Pin Assignments
5PB12xx Datasheet
GND
VDD
CLKIN
E_OSC
OE3
1
2
3
4
5
10 CLKOUT3
9 CLKOUT2
8 CLKOUT1
7 OE2
6 OE1
5PB1203 / 5PB1213
10-pin 2mm x 2mm DFN
16 15 1 4 13
OE2 1
12 VDD
 
20 19 18 17 16
OE2 1
15 VDD
VDD 2
11 CLKOUT2 OE3 2
14 CLKOUT3
GND 3 8XXXXXX 10 CLKOUT3 VDD 3
13 CLKOUT4
OE3 4
9 GND
56 7 8
GND 4
12 GND
OE6 5
11 CLKOUT5
6 7 8 9 10
5PB1204 / 5PB1214
16-pin, 2.5mm x 2.5mm VFQFPN
5PB1206 / 5PB1216
20-pin, 3mm x 3mm VFQFPN
Pin Descriptions
Pin Number
Pin Name 5PB1203 5PB1204 5PB1206
5PB1213 5PB1214 5PB1216
Pin Type
Pin Description
VDD
2
2, 7, 12
3, 9, 15
Power
Connect 1.8V to 5PB1203/5PB1204/5PB1206.
Connect 2.5V or 3.3V to 5PB1213/5PB1214/5PB1216.
GND
CLKIN
OE_OSC
OE1
OE2
OE3
OE4
OE5
OE6
CLKOUT1
CLKOUT2
CLKOUT3
CLKOUT4
CLKOUT5
CLKOUT6
1
3
4
6
7
5
8
9
10
3, 9, 14
15
6
16
1
4
5
13
11
10
8
4, 12, 18
20
8
19
1
2
6
7
5
17
16
14
13
11
10
Power
Input
Output
Input
Input
Input
Input
Input
Input
Output
Output
Output
Output
Output
Output
Power supply ground.
Reference input pin. Connect to LVCMOS input or TCXO.
Input Crystal Oscillator enable pin. Follow Enable Function Truth Table.
If all OE pins are low then OE_OSC is low. Otherwise OE_OSC is high,
enabling reference crystal oscillator.
Output Enable pin for CLKOUT1. Active High. Internal 120kΩ pull-down.
Output Enable pin for CLKOUT2. Active High. Internal 120kΩ pull-down.
Output Enable pin for CLKOUT3. Active High. Internal 120kΩ pull-down.
Output Enable pin for CLKOUT4. Active High. Internal 120kΩ pull-down.
Output Enable pin for CLKOUT5. Active High. Internal 120kΩ pull-down.
Output Enable pin for CLKOUT6. Active High. Internal 120kΩ pull-down.
Clock Output 1. Same frequency as CLKIN.
Clock Output 2. Same frequency as CLKIN.
Clock Output 3. Same frequency as CLKIN.
Clock Output 4. Same frequency as CLKIN.
Clock Output 5. Same frequency as CLKIN.
Clock Output 6. Same frequency as CLKIN.
©2020 Renesas Electronics Corporation
2




 5PB1204
5PB12xx Datasheet
Enable Function Truth Table
Input
Output
OE1 OE2 OE3 OE4 OE5 OE6 OE_OSC CLKOUT1 CLKOUT2 CLKOUT3 CLKOUT4 CLKOUT5 CLKOUT6
000000
0
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
1 0 0 0 0 0 1 CLOCK Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
1 1 0 0 0 0 1 CLOCK CLOCK Hi-Z Hi-Z Hi-Z Hi-Z
………………
1 1 1 1 1 1 1 CLOCK CLOCK CLOCK CLOCK CLOCK CLOCK
External Components
A minimum number of external components are required for proper operation. A decoupling capacitor of 0.01µF should be
connected between VDD on pin 1 and GND on pin 4, as close to the device as possible. A 33series terminating resistor
may be used on each clock output if the trace is longer than 1 inch.
To achieve the low output skew that the 5PB12xx is capable of, careful attention must be paid to board layout. Essentially,
all four outputs must have identical terminations, identical loads and identical trace geometries. If they do not, the output
skew will be degraded. For example, using a 30series termination on one output (with 33on the others) will cause at
least 15ps of skew.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 5PB12xx. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over
the recommended operating temperature range.
Item
Supply Voltage, VDD
Output Enable and All Inputs/Outputs
Ambient Operating Temperature (extended)
Storage Temperature
Junction Temperature
Soldering Temperature
Rating
3.8V
-0.5 V to VDD + 0.5 V
-40 to +105C
-65 to +150C
125C
260C
©2020 Renesas Electronics Corporation
3



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