CLOCK GENERATOR. IDT5V50009 Datasheet

IDT5V50009 GENERATOR. Datasheet pdf. Equivalent

Part IDT5V50009
Description SPREAD SPECTRUM CLOCK GENERATOR
Feature SPREAD SPECTRUM CLOCK GENERATOR DATASHEET IDT5V50009 Description The IDT5V50009 generates a low EM.
Manufacture Renesas
Datasheet
Download IDT5V50009 Datasheet



IDT5V50009
SPREAD SPECTRUM CLOCK GENERATOR
DATASHEET
IDT5V50009
Description
The IDT5V50009 generates a low EMI output clock and a
reference clock from a clock or crystal input. The part is
designed to lower EMI through the application of spreading
a clock. Using IDT’s proprietary mix of analog and digital
Phase-Locked Loop (PLL) technology, the device spreads
the frequency spectrum of the output, reducing the
frequency amplitude peaks by several dB depending on
spread range. The IDT5V50009 offers a range of down
spread from a high speed clock or crystal input. The
IDT5V50009 generates one modulated (SSCLK) and
unmodulated (REFCLK) clock. The modulated clock is
controlled by the select pin, and the unmodulated clock has
the same frequency as the input clock or crystal.
Features
Packaged in 8-pin SOIC
Available in Pb (lead) free package
Input frequency range 20- 40 MHz
Provides modulated and unmodulated clocks
Accepts a clock or crystal input
Provides down spread modulation
Provides power down function
Reduce electromagnetic interference (EMI) by
8-16 db
Operating voltage of 3.3 V
Advanced, low-power CMOS process
Block Diagram
VDD
PD
S0
X1/CLK
X2
External caps required for
with crystal for accurate
tuning of the clock
Clock Buffer/
Crystal
Ocsillator
PLL Clock
Synthesis and
Spread
Spectrum
Circuitry
GND
REFCLK
SSCLK
IDT™ SPREAD SPECTRUM CLOCK GENERATOR
1
IDT5V50009 REV C 040609



IDT5V50009
IDT5V50009
SPREAD SPECTRUM CLOCK GENERATOR
Pin Assignment
X1/ICLK
GND
S0
SSCLK
1
2
3
4
8 X2
7 VDD
6 PD
5 REFCLK
8 pin (150mil) SOIC
SSCG
Spread Percentage Select Table
S0 Spread
Spread
Direction
Percentage (%)
0 Down
1 Down
-1.25
-1.75
0 = connect to GND
1 = connect directly to VDD
* Default has internal pull up resistor to VDD
Pin Descriptions
Pin
Number
Pin Pin Type
Name
Pin Description
1 X1/ICLK Input Connect to a 20 to 40 MHz crystal or clock.
2 GND Power Connect to ground.
3 S0 Input Select spread percentage per table above. Weak Internal pull-up.
4 SSCLK Output Spread spectrum clock output per table above. Weak Internal Pull down
5 REFCLK Output CMOS level clock output matches the nominal frequency of the input crystal or clock.
Weak Internal Pull down
6 PD Input Power down tri-state. This pin powers down entire chip and tri-state the outputs when
low. Weak Internal pull-up.
7 VDD Power Connect to 3.3 V.
8 X2 Input Connect to a 20 to 40 MHz crystal or leave unconnected.
IDT™ SPREAD SPECTRUM CLOCK GENERATOR
2
IDT5V50009 REV C 040609





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