Buck Controller. TPS51116-EP Datasheet

TPS51116-EP Controller. Datasheet pdf. Equivalent

Part TPS51116-EP
Description Synchronous Buck Controller
Feature TPS51116-EP www.ti.com SLUSB52A – OCTOBER 2012 – REVISED NOVEMBER 2012 COMPLETE DDR, DDR2, DDR3, .
Manufacture etcTI
Datasheet
Download TPS51116-EP Datasheet



TPS51116-EP
TPS51116-EP
www.ti.com
SLUSB52A – OCTOBER 2012 – REVISED NOVEMBER 2012
COMPLETE DDR, DDR2, DDR3, AND LPDDR3 MEMORY POWER SOLUTION
SYNCHRONOUS BUCK CONTROLLER, 1-A LDO, BUFFERED REFERENCE
Check for Samples: TPS51116-EP
FEATURES
1
2 Synchronous Buck Controller (VDDQ)
– Wide-Input Voltage Range: 3.0-V to 28-V
– DCAP™ Mode with 100-ns Load Step
Response
– Current Mode Option Supports Ceramic
Output Capacitors
– Supports Soft-Off in S4/S5 States
– Current Sensing from RDS(on) or Resistor
– 2.5-V (DDR), 1.8-V (DDR2), Adjustable to
1.5-V (DDR3) or 1.2-V (LPDDR3) or
Output Range 0.75-V to 3.0-V
– Equipped with Powergood, Overvoltage
Protection and Undervoltage Protection
• 1-A LDO (VTT), Buffered Reference (VREF)
– Capable to Sink and Source 1 A
– LDO Input Available to Optimize Power
Losses
– Requires only 20-μF Ceramic Output
Capacitor
– Buffered Low Noise 10-mA VREF Output
– Accuracy ±20 mV for both VREF and VTT
– Supports High-Z in S3 and Soft-Off in S4/S5
– Thermal Shutdown
APPLICATIONS
• DDR/DDR2/DDR3/LPDDR3 Memory Power
Supplies
• SSTL-2, SSTL-18, SSTL-15 and HSTL
Termination
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
• Controlled Baseline
• One Assembly and Test Site
• One Fabrication Site
• Available in Military (–55°C to 125°C)
Temperature Range
• Extended Product Life Cycle
• Extended Product-Change Notification
• Product Traceability
DESCRIPTION
The TPS51116 provides a complete power supply for DDR/SSTL-2, DDR2/SSTL-18, DDR3/SSTL-15, and
LPDDR3 memory systems. It integrates a synchronous buck controller with a 1-A sink/source tracking linear
regulator and buffered low noise reference. The TPS51116 offers the lowest total solution cost in systems where
space is at a premium. The TPS51116 synchronous controller runs fixed 400-kHz, pseudo-constant frequency
PWM with an adaptive on-time control that can be configured in D-CAP™ Mode for ease of use and fastest
transient response or in current mode to support ceramic output capacitors. The 1-A sink/source LDO maintains
fast transient response only requiring 20-μF (2 × 10 μF) of ceramic output capacitance. In addition, the LDO
supply input is available externally to significantly reduce the total power losses. The TPS51116 supports all of
the sleep state controls placing VTT at high-Z in S3 (suspend to RAM) and discharging VDDQ, VTT and
VTTREF (soft-off) in S4/S5 (suspend to disk). TPS51116 has all of the protection features including thermal
shutdown and is offered in a 20-pin HTSSOP PowerPAD™ package.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
D-CAP, PowerPAD are trademarks of Texas Instruments.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated



TPS51116-EP
TPS51116-EP
SLUSB52A – OCTOBER 2012 – REVISED NOVEMBER 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
TA
–55°C to 125°C
ORDERING INFORMATION(1)
PACKAGE
ORDERABLE
PART NUMBER
Plastic HTSSOP PowerPAD (PWP)(2)
TPS51116MPWPREP
TPS51116MPWPEP
TOP-SIDE
MARKING
51116M
VID NUMBER
V62/12602-01XE
V62/12602-01XE-T
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) With Cu NIPDAU lead/ball finish
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range unless otherwise noted
VIN
VOUT
TJ
Tstg
VBST
Input voltage range
VBST wrt LL
CS, MODE, S3, S5, VTTSNS, VDDQSNS, V5IN, VLDOIN, VDDQSET
PGND, VTTGND
DRVH
Output voltage range
LL
LL, pulse width < 20 ns
COMP, DRVL, PGOOD, VTT, VTTREF
Maximum junction temperature
Storage temperature
MIN MAX UNIT
–0.3
36
–0.3
6
V
–0.3
6
–0.3
0.3
–1.0
36
–1.0
30
V
–5
30
–0.3
6
150
°C
–65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to the network ground terminal unless otherwise noted.
2
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Copyright © 2012, Texas Instruments Incorporated





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