FETs Converter. TPS51463 Datasheet

TPS51463 Converter. Datasheet pdf. Equivalent

Part TPS51463
Description FETs Converter
Feature TPS51463 www.ti.com SLUSAX2 – FEBRUARY 2012 3.3-V/5-V Input, D-CAP+™ Mode Synchronous Step-Down I.
Manufacture etcTI
Datasheet
Download TPS51463 Datasheet



TPS51463
TPS51463
www.ti.com
SLUSAX2 – FEBRUARY 2012
3.3-V/5-V Input, D-CAP+™ Mode Synchronous Step-Down Integrated FETs Converter
With 2-Bit VID
Check for Samples: TPS51463
FEATURES
1
23 Integrated FETs Converter w/TI Proprietary
D-CAP+™ Mode Architecture
• Minimum External Parts Count
• Support all MLCC Output Capacitor and
SP/POSCAP
• Auto Skip Mode
• Selectable 700-kHz and 1-MHz Frequency
• Small 4 mm × 4 mm, 24-Pin, QFN Package
APPLICATIONS
• Low-Voltage Applications Stepping Down from
5-V or 3.3-V Rail
• Notebook/Desktop Computers
• Intel® Chief River Platform ULV CPU System
Agent
DESCRIPTION
The TPS51463 is a fully integrated synchronous buck
regulator employing D-CAP+™. It is used for up to 5-
V step-down where system size is at its premium,
performance and optimized BOM are must-haves.
The TPS51463 fully supports the Intel® Chief River
platform, a ULV/CPU system agent application with
integrated 2-bit VID function.
The TPS51463 also features two switching frequency
settings (700 kHz and 1 MHz), skip mode, pre-bias
startup, programmable external capacitor soft-start
time/voltage transition time, output discharge, internal
VBST Switch, 2-V reference (±1%), power good and
enable.
The TPS51463 is available in a 4 mm × 4 mm, 24-
pin, QFN package (Green RoHs compliant and Pb
free) and is specified from -40°C to 85°C.
+5V
ENABLE
VID0
VID1
PGOOD
VIN
18 17 16 15 14 13
19 PGND
20 PGND
21 PGND
22 VIN
23 VIN
24 VIN
TPS51463
BST 12
SW 11
SW 10
SW 9
SW 8
SW 7
123456
VCCSA
VCCSASNS
UDG-12017
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
D-CAP+ is a trademark of Texas Instruments.
2
Intel is a registered trademark of Intel Corporation.
3
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated



TPS51463
TPS51463
SLUSAX2 – FEBRUARY 2012
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
TA
-40°C to 85°C
PACKAGE (2)
Plastic QFN
(RGE)
ORDERING INFORMATION(1)
ORDERING NUMBER
PINS
OUTPUT SUPPLY
TPS51463RGER
TPS51463RGET
24
Tape and reel
24
Mini reel
MINIMUM
QUANTITY
3000
250
ECO PLAN
Green (RoHS and
no Pb/Br)
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the TI
website at www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
THERMAL INFORMATION
θJA
θJCtop
θJB
ψJT
ψJB
θJCbot
THERMAL METRIC(1)
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
TPS51463
RGE (24) PIN
38.3
44.7
16
0.8
16.1
5.4
UNITS
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
VIN, EN, MODE
V5DRV, V5FILT, VBST (with respect to SW)
Input voltage range
VBST
VID0, VID1
VOUT
SW
SW (transient 20 ns and E=5 µJ)
Output voltage range COMP, SLEW, VREF
PGND
PGOOD
Human Body Model (HBM)
Electrostatic Discharge
Charged Device Model (CDM)
Storage temperature Tstg
Junction temperature TJ
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
VALUE
MIN
–0.3
–0.3
–0.3
–0.3
–1.0
–2.0
–3.5
–0.3
–0.3
–0.3
–55
–40
MAX
7.0
7.0
12.5
3.6
3.6
7.0
3.6
0.3
7.0
2000
500
150
150
300
UNIT
V
V
V
˚C
˚C
˚C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2
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Copyright © 2012, Texas Instruments Incorporated





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