8-Input Multiplexer. CD74HCT251 Datasheet

CD74HCT251 Multiplexer. Datasheet pdf. Equivalent

Part CD74HCT251
Description 8-Input Multiplexer
Feature Data sheet acquired from Harris Semiconductor SCHS169C November 1997 - Revised October 2003 CD54HC2.
Manufacture etcTI
Datasheet
Download CD74HCT251 Datasheet



CD74HCT251
Data sheet acquired from Harris Semiconductor
SCHS169C
November 1997 - Revised October 2003
CD54HC251, CD74HC251,
CD54HCT251, CD74HCT251
High-Speed CMOS Logic
8-Input Multiplexer, Three-State
[ /Title
(CD74
HC251
,
CD74
HCT25
1)
/Sub-
ject
(High
Speed
CMOS
Logic
8-Input
Multi-
plexer;
Three-
Features
Description
• Selects One of Eight Binary Data Inputs
• Three-State Output Capability
• True and Complement Outputs
• Typical (Data to Output) Propagation Delay of 14ns at
VCC = 5V, CL = 15pF, TA = 25oC
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• Alternate Source is Philips
The ’HC251 and ’HCT251 are 8-channel digital multiplexers
with three-state outputs, fabricated with high-speed silicon-
gate CMOS technology. Together with the low power
consumption of standard CMOS integrated circuits, they
possess the ability to drive 10 LSTTL loads. The three-state
feature makes them ideally suited for interfacing with bus
lines in a bus-oriented system.
This multiplexer features both true (Y) and complement (Y)
outputs as well as an output enable (OE) input. The OE must
be at a low logic level to enable this device. When the OE
input is high, both outputs are in the high-impedance state.
When enabled, address information on the data select inputs
determines which data input is routed to the Y and Y
outputs. The ’HCT251 logic family is speed, function, and
pin-compatible with the standard ’LS251.
Ordering Information
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il 1µA at VOL, VOH
PART NUMBER
CD54HC251F3A
CD54HCT251F3A
CD74HC251E
CD74HC251M
CD74HC251MT
CD74HC251M96
TEMP. RANGE
(oC)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
16 Ld CERDIP
16 Ld CERDIP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
Pinout
CD74HCT251E
-55 to 125
16 Ld PDIP
CD54HC251, CD54HCT251
(CERDIP)
CD74HC251, CD74HCT251
(PDIP, SOIC)
TOP VIEW
I3 1
I2 2
I1 3
I0 4
Y5
Y6
OE 7
GND 8
16 VCC
15 I4
14 I5
13 I6
12 I7
11 S0
10 S1
9 S2
CD74HCT251M
-55 to 125
16 Ld SOIC
CD74HCT251MT
-55 to 125
16 Ld SOIC
CD74HCT251M96
-55 to 125
16 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel of
250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1



CD74HCT251
CD54HC251, CD74HC251, CD54HCT251, CD74HCT251
Functional Diagram
OE
CHANNEL
INPUTS
I0 4
I1 3
I2 2
1
I3
15
I4
14
I5
13
I6
12
I7
DATA
SELECT
11
S0
10
S1
9
S2
7
5
Y
OUTPUTS
6
Y
TRUTH TABLE
INPUTS
OUTPUT
SELECT
OUTPUT
S2
S1
S0
CONTROL OE
Y
Y
X
X
X
H
Z
Z
L
L
L
L
I0
I0
L
L
H
L
I1
I1
L
H
L
L
I2
I2
L
H
H
L
I3
I3
H
L
L
L
I4
I4
H
L
H
L
I5
I5
H
H
L
L
I6
I6
H
H
H
L
I7
I7
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, Z = High Impedance
(Off), I0, I1...I7 = the level of the respective input.
2





@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)