Addressable Latch. CD74HCT259 Datasheet

CD74HCT259 Latch. Datasheet pdf. Equivalent

Part CD74HCT259
Description 8-Bit Addressable Latch
Feature CD54HC259, CD74HC259, CD54HCT259, CD74HCT259 Data sheet acquired from Harris Semiconductor SCHS173C.
Manufacture etcTI
Datasheet
Download CD74HCT259 Datasheet



CD74HCT259
CD54HC259, CD74HC259,
CD54HCT259, CD74HCT259
Data sheet acquired from Harris Semiconductor
SCHS173C
November 1997 - Revised October 2003
High-Speed CMOS Logic
8-Bit Addressable Latch
[ /Title
(CD74
HC259
,
CD74
HCT25
9)
/Sub-
ject
(High
Speed
CMOS
Logic
8-Bit
Addres
sable
Latch)
Features
Description
• Buffered Inputs and Outputs
• Four Operating Modes
Typical Propagation Delay
CL = 15pF, TA = 25oC
of
15ns
at
VCC
=
5V,
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il 1µA at VOL, VOH
The ’HC259 and ’HCT259 Addressable Latch features the
low-power consumption associated with CMOS circuitry and
has speeds comparable to low-power Schottky.
This latches three active modes and one reset mode. When
both the Latch Enable (LE) and Master Reset (MR) inputs are
low (8-line Demultiplexer mode) the output of the addressed
latch follows the Data input and all other outputs are forced
low. When both MR and LE are high (Memory Mode), all
outputs are isolated from the Data input, i.e., all latches hold
the last data presented before the LE transition from low to
high. A condition of LE low and MR high (Addressable Latch
mode) allows the addressed latch’s output to follow the data
input; all other latches are unaffected. The Reset mode (all
outputs low) results when LE is high and MR is low.
Ordering Information
PART NUMBER
CD54HC259F3A
CD54HCT259F3A
CD74HC259E
CD74HC259M
TEMP. RANGE
(oC)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
16 Ld CERDIP
16 Ld CERDIP
16 Ld PDIP
16 Ld SOIC
CD74HC259MT
-55 to 125
16 Ld SOIC
CD74HC259M96
-55 to 125
16 Ld SOIC
CD74HCT259E
-55 to 125
16 Ld PDIP
CD74HCT259M
-55 to 125
16 Ld SOIC
CD74HCT259MT
-55 to 125
16 Ld SOIC
CD74HCT259M96
-55 to 125
16 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel
of 250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1



CD74HCT259
Pinout
CD54HC259, CD74HC259, CD54HCT259, CD74HCT259
CD54HC259, CD54HCT259
(CERDIP)
CD74HC259, CD74HCT259
(PDIP, SOIC)
TOP VIEW
A0 1
A1 2
A2 3
Q0 4
Q1 5
Q2 6
Q3 7
GND 8
16 VCC
15 MR
14 LE
13 D
12 Q7
11 Q6
10 Q5
9 Q4
Functional Diagram
1
A0
A1
2
1-OF-8
DECODER
3
A2
14
LE
15
MR
13
D
8
LATCHES
4
Q0
5
Q1
6
Q2
7
Q3
9
Q4
10
Q5
11
Q6
12
Q7
GND = 8
VCC = 16
TRUTH TABLE
INPUTS
MR LE
OUTPUT OF
ADDRESS
LATCH
EACH OTHER
OUTPUT
FUNCTION
HL
D
Qio
Addressable
Latch
HH
Qio
LL
D
Qio
Memory
L
8-Line
Demultiplexer
LH
L
L
Reset
H = High Voltage Level
L = Low Voltage Level
D = The level at the data input
Qio = The level of Qi (i = 0, 1...7, as appropriate) before the indicat-
ed steady-state input conditions were established.
LATCH SELECTION TABLE
SELECT INPUTS
A2
A1
A0
L
L
L
L
L
H
L
H
L
L
H
H
H
L
L
H
L
H
H
H
L
H
H
H
LATCH
ADDRESSED
0
1
2
3
4
5
6
7
2





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