LDO Regulator. NCP167 Datasheet

NCP167 Regulator. Datasheet pdf. Equivalent

Part NCP167
Description LDO Regulator
Feature NCP167 LDO Regulator - Ultra-Low Noise, High PSRR, RF and Analog Circuits 700 mA The NCP167 is a li.
Manufacture ON Semiconductor
Datasheet
Download NCP167 Datasheet



NCP167
NCP167
LDO Regulator - Ultra-Low
Noise, High PSRR, RF and
Analog Circuits
700 mA
The NCP167 is a linear regulator capable of supplying 700 mA
output current. Designed to meet the requirements of RF and analog
circuits, the NCP167 device provides low noise, high PSRR, low
quiescent current, and very good load/line transients. The device is
designed to work with a 1 mF input and a 1 mF output ceramic capacitor.
It is available in two thickness ultrasmall 0.35P, 0.65 mm x 0.65 mm
Chip Scale Package (CSP) and XDFN4 0.65P, 1 mm x 1 mm.
Features
Operating Input Voltage Range: 1.9 V to 5.5 V
Available in Fixed Voltage Option: 1.8 V to 5.2 V
±2% Accuracy Over Load/Temperature
Ultra Low Quiescent Current Typ. 12 mA
Standby Current: Typ. 0.1 mA
Very Low Dropout: 210 mV at 700 mA
Ultra High PSRR: Typ. 85 dB at 20 mA, f = 1 kHz
Ultra Low Noise: 8.5 mVRMS
Stable with a 1 mF Small Case Size Ceramic Capacitors
Available in WLCSP4 0.65 mm x 0.65 mm x 0.33 mm
XDFN4 1 mm x 1 mm x 0.4 mm
These Devices are PbFree, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
Batterypowered Equipment
Wireless LAN Devices
Smartphones, Tablets
Cameras, DVRs, STB and Camcorders
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WLCSP4
CASE 567JZ
MARKING
DIAGRAMS
XM
A1
1
XDFN4
CASE 711AJ
XX M
1
X or XX = Specific Device Code
M
= Date Code
PIN CONNECTIONS
IN OUT
A1 A2
B1 B2
EN GND
(Top View)
VIN
IN
OUT
CIN
1 mF
Ceramic
ON
OFF
NCP167
EN
GND
VOUT
COUT
1 mF
Ceramic
(Top View)
Figure 1. Typical Application Schematics
ORDERING INFORMATION
See detailed ordering and shipping information on page 10 of
this data sheet.
© Semiconductor Components Industries, LLC, 2016
1
September, 2019 Rev. 3
Publication Order Number:
NCP167/D



NCP167
IN
EN
NCP167
BANDGAP
REFERENCE
ENABLE
LOGIC
INTEGRATED
SOFTSTART
THERMAL
SHUTDOWN
MOSFET
DRIVER WITH
CURRENT LIMIT
OUT
* ACTIVE DISCHARGE
Version A only
EN
GND
Figure 2. Simplified Schematic Block Diagram
PIN FUNCTION DESCRIPTION
Pin No.
CSP4
Pin No.
XDFN4
Pin
Name
Description
A1
4
IN
Input voltage supply pin
A2
1
OUT Regulated output voltage. The output should be bypassed with small 1 mF ceramic capacitor.
B1
3
EN
Chip enable: Applying VEN < 0.4 V disables the regulator, Pulling VEN > 1.2 V enables the LDO.
B2
2
GND Common ground connection
EPAD
EPAD Expose pad should be tied to ground plane for better power dissipation
ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Input Voltage (Note 1)
VIN
0.3 V to 6
V
Output Voltage
VOUT
0.3 to VIN + 0.3, max. 6 V
V
Chip Enable Input
VCE
0.3 to VIN + 0.3, max. 6 V
V
Output Short Circuit Duration
tSC
unlimited
s
Maximum Junction Temperature
TJ
150
°C
Storage Temperature
TSTG
55 to 150
°C
ESD Capability, Human Body Model (Note 2)
ESDHBM
2000
V
ESD Capability, Machine Model (Note 2)
ESDMM
200
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per EIA/JESD22A114
ESD Machine Model tested per EIA/JESD22A115
Latchup Current Maximum Rating tested per JEDEC standard: JESD78.
THERMAL CHARACTERISTICS
Rating
Symbol
Value
Thermal Characteristics, WLCSP4 (Note 3)
Thermal Resistance, JunctiontoAir
Thermal Characteristics, XDFN4 (Note 3)
Thermal Resistance, JunctiontoAir
108
RqJA
198
3. Measured according to JEDEC board specification. Detailed description of the board can be found in JESD517
Unit
°C/W
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