master transceiver. TJA1124 Datasheet

TJA1124 transceiver. Datasheet pdf. Equivalent

Part TJA1124
Description Quad LIN master transceiver
Feature TJA1124 Quad LIN master transceiver Rev. 1 — 8 May 2018 Product data sheet 1 General description T.
Manufacture NXP
Datasheet
Download TJA1124 Datasheet



TJA1124
TJA1124
Quad LIN master transceiver
Rev. 1 — 8 May 2018
Product data sheet
1 General description
The TJA1124 is a quad Local Interconnect Network (LIN) master channel device.
It provides the interface between a LIN master protocol controller and the physical
bus in a LIN network. Each of the four channels contains a LIN transceiver and LIN
master termination. The TJA1124 is primarily intended for in-vehicle subnetworks using
baud rates up to 20 kBd and is compliant with LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2A,
ISO 17987-4:2016 (12 V LIN) and SAE J2602-1.
The transmit data streams generated by the LIN master protocol controller are converted
by the TJA1124 into optimized bus signals shaped to minimize ElectroMagnetic Emission
(EME). The LIN bus output pins are pulled HIGH via internal LIN master termination
resistors. The receivers detect receive data streams on the LIN bus input pins and
transfer them to the microcontroller via pins RXD1 to RXD4.
Power consumption is very low in Low Power mode. However, the TJA1124 can still be
woken up via pins SLP and LIN1 to LIN4.
2 Features and benefits
2.1 General
Four LIN master channels in a single package:
LIN transceiver
LIN master termination consisting of a diode and a 1 kΩ ±10 % resistor
Compliant with:
LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2A
ISO 17987-4:2016 (12 V LIN)
SAE J2602-1
Very low current consumption in Low Power mode with wake-up via SLP or LIN pins
Option to control an external voltage regulator via the INHN output
Bus signal shaping optimized for baud rates up to 20 kBd
VIO input for direct interfacing with 3.3 V and 5 V microcontrollers
Passive behavior in unpowered state
Undervoltage detection
K-line compatible
Leadless DHVQFN24 package (3.5 mm × 5.5 mm) supporting improved Automated
Optical Inspection (AOI) capability
2.2 Protection
Excellent ElectroMagnetic Immunity (EMI)



TJA1124
NXP Semiconductors
TJA1124
Quad LIN master transceiver
Very high ESD robustness: ±6 kV according to IEC61000-4-2 for pins LIN1 to LIN4 and
BAT
Bus terminal and battery pin protected against transients in the automotive environment
(ISO 7637)
Bus terminal short-circuit proof to battery and ground
TXD dominant timeout function
LIN dominant timeout function
Thermal protection
3 Ordering information
Table 1. Ordering information
Type number Package
TJA1124AHG[1]
TJA1124BHG[2]
Name
Description
DHVQFN24 plastic dual in-line compatible thermal enhanced very thin quad flat
package; no leads; 24 terminals; body 3.5 × 5.5 × 0.85 mm
[1] The LIN master termination of TJA1124AHG is enabled in Low Power mode.
[2] The LIN master termination of TJA1124BHG is disabled in Low Power mode
Version
SOT 815-1
4 Block diagram
TJA1124
VIO
UNDERVOLTAGE
DETECTION
UNDERVOLTAGE
DETECTION
VOLTAGE
REFERENCE
BAT
LIN CHANNEL 1
LIN TRANSCEIVER
VBAT
SLP
LIN
TRANSCEIVER
CONTROL
TXD1
RXD1
TXD2
RXD2
TXD3
RXD3
TXD4
RXD4
INHN
SYSTEM
CONTROL
LIN CHANNEL 2
LIN CHANNEL 3
LIN CHANNEL 4
TEMPERATURE
PROTECTION
Figure 1. Block diagram
TJA1124
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 8 May 2018
LIN1
LIN2
LIN3
LIN4
GND
aaa-029893
© NXP B.V. 2018. All rights reserved.
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