Channel Repeater. DS100BR410 Datasheet

DS100BR410 Repeater. Datasheet pdf. Equivalent

Part DS100BR410
Description Low Power Quad Channel Repeater
Feature DS100BR410 www.ti.com SNLS326B – OCTOBER 2010 – REVISED APRIL 2013 DS100BR410 Low Power Quad Chan.
Manufacture etcTI
Datasheet
Download DS100BR410 Datasheet




DS100BR410
DS100BR410
www.ti.com
SNLS326B – OCTOBER 2010 – REVISED APRIL 2013
DS100BR410 Low Power Quad Channel Repeater with 10.3125 Gbps Equalizer and De-
Emphasis Driver
Check for Samples: DS100BR410
FEATURES
1
2 Quad channel repeater for up to 10.3125 Gbps
• Low power consumption, with option to power
down unused channels
• Adjustable receive equalization
• Adjustable transmit de-emphasis
• Adjustable transmit VOD (up to 1200 mVp-p)
• IDLE detection — squelch function auto mutes
the output for SATA/SAS OOB signal
• <0.22 UI of residual DJ at 10.3125 Gbps with 12
meters cable
• Programmable via pin selection or SMBus
interface
• Single supply operation at 2.5 V ±5%
• -40°C to +85°C Operation
7 kV HBM ESD Rating
• High speed signal flow–thru pinout package:
48-pin WQFN (7 mm x 7 mm, 0.5 mm pitch)
APPLICATIONS
• High-speed active copper cable modules
• FR-4 Backplanes
• 10GE, 8GFC, 10GFC, 10G SONET, SAS, SATA,
and InfiniBand
DESCRIPTION
The DS100BR410 is an extremely low power, high
performance quad-channel repeater for high-speed
serial links with data rates up to 10.3125 Gbps. The
device performs both receive equalization and
transmit de-emphasis on each of its 4 channels to
compensate for channel loss, allowing maximum
flexibility of physical placement within a system.
The receiver's continuous time linear equalizer
(CTLE) is capable of opening an input eye that is
completely closed due to inter-symbol interference
(ISI) induced by the interconnect medium such as
backplane trace or cable. The transmitter features
adjustable VOD (output amplitude voltage level) and
de-emphasis driver to compensate for PCB trace lost.
With a low power consumption and control to turn-off
unused channels, the DS100BR410 is part of TI's
PowerWise family of energy efficient devices.
The programmable settings can be applied via pin
mode or SMBus mode interface.
Typical Application Diagram
ASIC/
FPGA
DS100BR410
Slice 1 of 4
Interconnect Cable
DS100BR410
Slice 1 of 4
ASIC/
FPGA
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2013, Texas Instruments Incorporated



DS100BR410
DS100BR410
SNLS326B – OCTOBER 2010 – REVISED APRIL 2013
Connection Diagram
IN_0+ 1
IN_0- 2
VDD 3
IN_1+ 4
IN_1- 5
VDD 6
VDD 7
IN_2+ 8
IN_2- 9
VDD 10
IN_3+ 11
IN_3- 12
DS100BR410
TOP VIEW
DAP = GND
36 OUT_0+
35 OUT_0-
34 GND
33 OUT_1+
32 OUT_1-
31 GND
30 GND
29 OUT_2+
28 OUT_2-
27 GND
26 OUT_3+
25 OUT_3-
www.ti.com
Pin Name
Pin #
I/O, Type(1)
HIGH SPEED DIFFERENTIAL I/O
IN_0+
IN_0–
1
I, CML
2
IN_1+
IN_1–
4
I, CML
5
IN_2+
IN_2–
8
I, CML
9
IN_3+
IN_3–
11
I, CML
12
OUT_0+
OUT_0–
36
O, CML
35
OUT_1+
OUT_1–
33
O, CML
32
OUT_2+
OUT_2–
29
O, CML
28
OUT_3+
OUT_3–
26
O, CML
25
2.5V LVCMOS CONTROL PINS
BST_2
BST_1
BST_0
37
I, LVCMOS
14
23
EN0
44
I, LVCMOS
EN1
42
EN2
40
EN3
38
Pin Descriptions
Description
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100
terminating resistor connects IN_0+ to IN_0-.
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100
terminating resistor connects IN_1+ to IN_1-.
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100
terminating resistor connects IN_2+ to IN_2-.
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100
terminating resistor connects IN_3+ to IN_3-.
Inverting and non-inverting CML differential outputs from the driver. An on-chip 100
terminating resistor connects OUT_0+ to OUT_0-.
Inverting and non-inverting CML differential outputs from the driver. An on-chip 100
terminating resistor connects OUT_1+ to OUT_1-.
Inverting and non-inverting CML differential outputs from the driver. An on-chip 100
terminating resistor connects OUT_2+ to OUT_2-.
Inverting and non-inverting CML differential outputs from the driver. An on-chip 100
terminating resistor connects OUT_3+ to OUT_3-.
BST_2, BST_1, and BST_0 select the equalizer boost level for all channels.
BST_2 and BST_1 are internally pulled high.
BST_0 is internally pulled low. See Table 1
Enable channel n input.
When held High, normal operation is selected.
When held Low, standby mode is selected.
EN is internally pulled High.
(1) Note: I = Input O = Output, LVCMOS pins are 2.5 V levels only, only SMBus pins SDA, SDC and CS are 3.3V tolerant.
2
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