2:1/1:2 Mux/Buffer. DS100MB201 Datasheet

DS100MB201 Mux/Buffer. Datasheet pdf. Equivalent

Part DS100MB201
Description Dual Lane 2:1/1:2 Mux/Buffer
Feature DS100MB201 www.ti.com SNLS333A – APRIL 2011 – REVISED APRIL 2013 DS100MB201 Dual Lane 2:1/1:2 Mux.
Manufacture etcTI
Datasheet
Download DS100MB201 Datasheet




DS100MB201
DS100MB201
www.ti.com
SNLS333A – APRIL 2011 – REVISED APRIL 2013
DS100MB201 Dual Lane 2:1/1:2 Mux/Buffer with Equalization
Check for Samples: DS100MB201
FEATURES
1
2 Up to 10.3125 Gbps
• Dual Lane 2:1 Mux, 1.2 Switch or Fanout
• Adjustable Transmit Differential Output
Voltage (VOD)
• <0.3 UI of Residual DJ at 10.3125 Gbps with
10” FR4 trace
• Adjustable Electrical IDLE Detect Threshold
• Signal Conditioning Programmable through
SMBus I/F
• Single 2.5V Supply Operation
• >6 kV HBM ESD Rating
• 3.3V Tolerant SMBus Interface
• High Speed Signal flow–thru Pinout
• Package: 54-pin WQFN (10 mm x 5.5 mm)
APPLICATIONS
• XAUI (3.125 Gbps), RXAUI (6.25 Gbps)
• sRIO – Serial Rapid I/O
• Fibre Channel (8.5 Gbps)
• 10GBase-CX4, InfiniBand (QDR, SDR & DDR)
• FR4 Backplane Traces
DESCRIPTION
The DS100MB201 is a dual lane 2:1 multiplexer and
1:2 switch or fan-out buffer with signal conditioning
suitable for 10GE, Fibre Channel, Infiniband,
SATA/SAS and other high-speed bus applications up
to 10.31215 Gbps. The device performs receive
equalization allowing maximum flexibility of physical
placement within a system. The receiver's continuous
time linear equalizer (CTLE) provides a boost to
compensate for 10” of 4 mil FR4 stripline at 10.3125
Gbps. The DS100MB201 is capable of opening an
input eye that is completely closed due to inter-
symbol interference (ISI) induced by the interconnect
medium. The transmitter features a programmable
amplitude voltage levels to be selected from 600
mVp-p to 800 mVp-p. The signal conditioning settings
are programmable with register control.
With a typical power consumption of 100 mW/channel
at 10.3125 Gbps, and SMBus register control to turn-
off unused lanes, the DS100MB201 is part of TI's
PowerWise family of energy efficient devices.
Typical Application
HDD0
RX
TX
SEL0
Cs > 10 nF 2
2
DS100MB201
DOUT0+-
SIA0+-
SIB0+-
Cs > 10 nF 2
2
HDD1
2
RX
2
TX
SIA1+-
2
DOUT1+-
SIB1+-
2
SOA0+-
2
DIN0+-
SOB0+-
2
SOA1+-
2
DIN1+-
SOB1+-
2
SEL1
TXA
TXB
TXA
TXB
SATA/SAS
Controller
RXA
RXB
RXA
RXB
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2013, Texas Instruments Incorporated



DS100MB201
DS100MB201
SNLS333A – APRIL 2011 – REVISED APRIL 2013
Pin Diagram
SMBUS AND CONTROL
NC 1
NC 2
DOUT0+ 3
DOUT0- 4
NC 5
NC 6
DOUT1+ 7
DOUT1- 8
VDD 9
DIN0+ 10
DIN0- 11
NC 12
NC 13
VDD 14
DIN1+ 15
DIN1- 16
NC 17
NC 18
TOP VIEW
DAP = GND
45 SIA0+
44 SIA0-
43 SIB0+
42 SIB0-
41 VDD
40 SIA1+
39 SIA1-
38 SIB1+
37 SIB1-
36 VDD
35 SOA0+
34 SOA0-
33 SOB0+
32 SOB0-
31 SOA1+
30 SOA1-
29 SOB1+
28 SOB1-
www.ti.com
Figure 1. DS100MB201 Pin Diagram 54L WQFN Package
See Package Number NJY0054A
Pin Name
Pin Number
Differential High Speed I/O's
SIA0+, SIA0-,
SIA1+, SIA1-
45, 44,
40, 39
SOA0+, SOA0-,
SOA1+, SOA1-
SIB0+, SIB0-,
SIB1+, SIB1-
35, 34,
31, 30
43, 42,
38, 37
SOB0+, SOB0-,
SOB1+, SOB1-
DIN0+, DIN0-,
DIN1+, DIN1-
33, 32,
29, 28
10, 11,
15, 16
PIN DESCRIPTIONS(1)
I/O, Type (2) (3) (4)
Pin Description
I, CML
O
I, CML
O
I, CML
Inverting and non-inverting CML differential inputs to the equalizer. A gated on-
chip 50Ω termination resistor connects SIA_n+ to VDD and SIA_n- to VDD
when enabled.
Inverting and non-inverting low power differential signaling 50Ω outputs. Fully
compatible with AC coupled CML inputs.
Inverting and non-inverting CML differential inputs to the equalizer. A gated on-
chip 50Ω termination resistor connects SIB_n+ to VDD and SIB_n- to VDD
when enabled.
Inverting and non-inverting low power differential signaling 50Ω outputs. Fully
compatible with AC coupled CML inputs.
Inverting and non-inverting CML differential inputs to the equalizer. A gated on-
chip 50Ω termination resistor connects SIB_n+ to VDD and SIB_n- to VDD
when enabled.
(1) 1 = HIGH, 0 = LOW, FLOAT = 3rd input state.
(2) FLOAT condition; Do not drive pin; pin is internally biased to mid level with 50 kΩ pull-up/pull-down.
(3) Internal pulled-down = Internal 30 kΩ pull-down resistor to GND is present on the input.
(4) Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%.
2
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