8-LINE DECODERS/DEMULTIPLEXER. SN74LV138A Datasheet

SN74LV138A DECODERS/DEMULTIPLEXER. Datasheet pdf. Equivalent

Part SN74LV138A
Description 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXER
Feature www.ti.com FEATURES • 2-V to 5.5-V VCC Operation • Max tpd of 9.5 ns at 5 V • Typical VOLP (Output G.
Manufacture etcTI
Datasheet
Download SN74LV138A Datasheet




SN74LV138A
www.ti.com
FEATURES
2-V to 5.5-V VCC Operation
Max tpd of 9.5 ns at 5 V
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 3.3 V, TA = 25°C
Support Mixed-Mode Voltage Operation on All
Ports
SN54LV138A, SN74LV138A
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCLS395L – APRIL 1998 – REVISED AUGUST 2005
Ioff Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
SN54LV138A . . . J OR W PACKAGE
SN74LV138A . . . D, DB, DGV, NS
OR PW PACKAGE
(TOP VIEW)
SN74LV138A . . . RGY PACKAGE
(TOP VIEW)
SN54LV138A . . . FK PACKAGE
(TOP VIEW)
A1
B2
C3
G2A 4
G2B 5
G1 6
Y7 7
GND 8
16 VCC
15 Y0
14 Y1
13 Y2
12 Y3
11 Y4
10 Y5
9 Y6
1
B2
C3
G2A 4
G2B 5
G1 6
Y7 7
8
16
15 Y0
14 Y1
13 Y2
12 Y3
11 Y4
10 Y5
9
3 2 1 20 19
C4
18 Y1
G2A 5
17 Y2
NC 6
16 NC
G2B 7
15 Y3
G1 8
14 Y4
9 10 11 12 13
NC − No internal connection
DESCRIPTION/ORDERING INFORMATION
The 'LV138A devices are 3-line to 8-line decoders/demultiplexers designed for 2-V to 5.5-V VCC operation.
TA
–40°C to 85°C
–55°C to 125°C
ORDERING INFORMATION
PACKAGE (1)
ORDERABLE PART NUMBER
QFN – RGY
Reel of 1000
SN74LV138ARGYR
SOIC – D
Tube of 40
Reel of 2500
SN74LV138AD
SN74LV138ADR
SOP – NS
Reel of 2000
SN74LV138ANSR
SSOP – DB
Reel of 2000
SN74LV138ADBR
Tube of 90
SN74LV138APW
TSSOP – PW
Reel of 2000
SN74LV138APWR
Reel of 250
SN74LV138APWT
TVSOP – DGV
Reel of 2000
SN74LV138ADGVR
CDIP – J
Tube of 25
SNJ54LV138AJ
CFP – W
Tube of 150
SNJ54LV138AW
LCCC – FK
Tube of 55
SNJ54LV138AFK
TOP-SIDE MARKING
LV138A
LV138A
74LV138A
LV138A
LV138A
LV138A
SNJ54LV138AJ
SNJ54LV138AW
SNJ54LV138AFK
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRO-
DUCTION DATA information current as of publication date. Prod-
ucts conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily
include testing of all parameters.
Copyright © 1998–2005, Texas Instruments Incorporated



SN74LV138A
SN54LV138A, SN74LV138A
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCLS395L – APRIL 1998 – REVISED AUGUST 2005
www.ti.com
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
These devices are designed for high-performance memory-decoding or data-routing applications requiring very
short propagation delay times. In high-performance memory systems, these decoders can be used to minimize
the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the
delay times of these decoders and the enable time of the memory usually are less than the typical access time of
the memory. This means that the effective system delay introduced by the decoder is negligible.
The conditions at the binary-select inputs (A, B, C) and the three enable inputs (G1, G2A, G2B) select one of
eight output lines. The two active-low (G2A, G2B) and one active-high (G1) enable inputs reduce the need for
external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters
and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing
applications.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the devices when they are powered down.
FUNCTION TABLE
ENABLE INPUTS SELECT INPUTS
OUTPUTS
G1 G2A G2B C
B
A Y0 Y1 Y20 Y3 Y4 Y5 Y6 Y7
X
H
X
X
X
X
H
H
H
H
H
H
H
H
X
X
H
X
X
X
H
H
H
H
H
H
H
H
L
X
X
X
X
X
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
L
H
H
H
H
H
H
H
L
L
L
H
L
H
H
L
H
H
H
H
H
H
L
L
L
H
H
H
H
H
L
H
H
H
H
H
L
L
H
L
L
H
H
H
H
L
H
H
H
H
L
L
H
L
H
H
H
H
H
H
L
H
H
H
L
L
H
H
L
H
H
H
H
H
H
L
H
H
L
L
H
H
H
H
H
H
H
H
H
H
L
2







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