D/A Converter. DAC8568 Datasheet

DAC8568 Converter. Datasheet pdf. Equivalent

Part DAC8568
Description D/A Converter
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DAC8568
Product
Folder
Order
Now
Technical
Documents
Tools &
Software
Support &
Community
DAC7568, DAC8168, DAC8568
SBAS430F – JANUARY 2009 – REVISED APRIL 2018
DAC7568, DAC8168, DAC8568 12-/14-/16-Bit, Octal-Channel, Ultralow Glitch, Voltage
Output, Digital-to-Analog Converters with 2.5-V 2-ppm/°C Internal Reference
1 Features
1 Relative Accuracy:
– DAC7568 (12-Bit): 0.3 LSB INL
– DAC8168 (14-Bit): 1 LSB INL
– DAC8568 (16-Bit): 4 LSB INL
• Glitch Energy: 0.1nV-s
• Internal Reference:
– 2.5V Reference Voltage (disabled by default)
– 0.004% Initial Accuracy (typ)
– 2ppm/°C Temperature Drift (typ)
– 5ppm/°C Temperature Drift (max)
– 20mA Sink/Source Capability
• Power-On Reset to Zero Scale or Midscale
• Ultralow Power Operation: 1.25mA at 5V Including
Internal Reference Current
• Wide Power-Supply Range: +2.7V to +5.5V
• Monotonic Over Entire Temperature Range
• Low-Power Serial Interface with Schmitt-Triggered
Inputs: Up to 50MHz
• On-Chip Output Buffer Amplifier with Rail-to-Rail
Operation
• Temperature Range: –40°C to +125°C
2 Applications
• Portable Instrumentation
• Closed-Loop Servo-Control/Process Control
• Data Acquisition Systems
• Programmable Attenuation, Digital Gain, and
Offset Adjustment
• Programmable Voltage and Current Sources
3 Description
The DAC7568, DAC8168, and DAC8568 are low-
power, voltage-output, eight-channel, 12-, 14-, and
16-bit digital-to-analog converters (DACs),
respectively. These devices include a 2.5V, 2ppm/°C
internal reference (disabled by default), giving a full-
scale output voltage range of 2.5V or 5V. The internal
reference has an initial accuracy of 0.004% and can
source up to 20mA at the VREFIN/VREFOUT pin.
These devices are monotonic, providing excellent
linearity and minimizing undesired code-to-code
transient voltages (glitch). They use a versatile 3-wire
serial interface that operates at clock rates up to
50MHz. The interface is compatible with standard
SPI™, QSPI™, Microwire™, and digital signal
processor (DSP) interfaces.
1
The DAC7568, DAC8168, and DAC8568 incorporate
a power-on-reset circuit that ensures the DAC output
powers up at either zero scale or midscale until a
valid code is written to the device. These devices
contain a power-down feature, accessed over the
serial interface, that reduces current consumption to
typically 0.18μA at 5V. Power consumption (including
internal reference) is typically 2.9mW at 3V, reducing
to less than 1μW in power-down mode. The low
power consumption, internal reference, and small
footprint make these devices ideal for portable,
battery-operated equipment.
The DAC7568, DAC8168, and DAC8568 are drop-in
and function-compatible with each other, and are
available in TSSOP-16 and TSSOP-14 packages.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
DAC7568
TSSOP (14)
TSSOP (16)
5.00 mm x 4.40 mm
5.00 mm x 4.40 mm
DAC8168
TSSOP (14)
TSSOP (16)
5.00 mm x 4.40 mm
5.00 mm x 4.40 mm
DAC8568
TSSOP (16)
5.00 mm x 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
AVDD
DAC7568
DAC8168
DAC8568
SYNC
SCLK
DIN
32-Bit Shift Register
GND
Block Diagram
Data Buffer H
Data Buffer G
Data Buffer F
Data Buffer E
Data Buffer D
Data Buffer C
Data Buffer B
Data Buffer A
DAC Register H
DAC Register G
DAC Register F
DAC Register E
DAC Register D
DAC Register C
DAC Register B
DAC Register A
Buffer Control
Register Control
Control Logic
LDAC
CLR
VREFIN/VREFOUT
2.5V
Reference
12-/14-/16-Bit
DAC
12-/14-/16-Bit
DAC
12-/14-/16-Bit
DAC
12-/14-/16-Bit
DAC
12-/14-/16-Bit
DAC
12-/14-/16-Bit
DAC
12-/14-/16-Bit
DAC
12-/14-/16-Bit
DAC
VOUTH
VOUTG
VOUTF
VOUTE
VOUTD
VOUTC
VOUTB
VOUTA
Power-Down
Control Logic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.



DAC8568
DAC7568, DAC8168, DAC8568
SBAS430F – JANUARY 2009 – REVISED APRIL 2018
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Device Comparison Table..................................... 3
6 Pin Configuration and Functions ......................... 4
7 Specifications......................................................... 5
7.1 Absolute Maximum Ratings .................................... 5
7.2 Electrical Characteristics.......................................... 5
7.3 Timing Requirements ............................................... 7
7.4 Typical Characteristics: Internal Reference .............. 9
7.5 Typical Characteristics: DAC at AVDD = 5.5 V........ 11
7.6 Typical Characteristics: DAC at AVDD = 3.6 V........ 21
7.7 Typical Characteristics: DAC at AVDD = 2.7 V........ 23
8 Detailed Description ............................................ 31
8.1 Functional Block Diagram ....................................... 31
8.2 Feature Description................................................. 31
8.3 Device Functional Modes........................................ 44
9 Application and Implementation ........................ 48
9.1 Application Information............................................ 48
9.2 Typical Applications - Microprocessor Interfacing... 48
10 Layout................................................................... 53
10.1 Layout Guidelines ................................................. 53
11 Device and Documentation Support ................. 54
11.1 Device Support .................................................... 54
11.2 Related Links ........................................................ 57
11.3 Receiving Notification of Documentation Updates 57
11.4 Community Resources.......................................... 57
11.5 Trademarks ........................................................... 57
11.6 Electrostatic Discharge Caution ............................ 57
11.7 Glossary ................................................................ 57
12 Mechanical, Packaging, and Orderable
Information ........................................................... 58
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (January 2014) to Revision F
Page
• Updated data sheet to SDS standard .................................................................................................................................... 1
• Added External reference current grades and updated typ values ....................................................................................... 6
• Added Reference input impedance grades and updated typ values ..................................................................................... 6
• Changed IDD Normal mode, internal reference switched on, AVDD = 3.6V to 5.5V, VINH = AVDD and VINL = GND
maximum value from 2.0mA to 2.5mA ................................................................................................................................... 7
Changes from Revision D (May 2012) to Revision E
Page
• Changed bit value in last three rows of Power-Down Commands section in from '0' to '1' ................................................. 38
Changes from Revision C (February 2011) to Revision D
Page
• Changed Logic Input HIGH Voltage parameter test condition into two rows ......................................................................... 7
Changes from Revision B (November 2010) to Revision C
Page
• Changed Output Voltage parameter min/max values from 2.4895 and 2.5005 to 2.4975 and 2.5025, respectively............. 6
• Changed Initial Accuracy parameter min/max values from –0.02 and 0.02 to –0.1 and 0.1, respectively ............................ 6
Changes from Revision A (April 2009) to Revision B
Page
• Changed Logic Input LOW Voltage parameter maximum value from 0.8 to 0.3 × AVDD ....................................................... 7
• Changed Logic Input HIGH Voltage parameter minimum value from 1.8 to 0.7 × AVDD ....................................................... 7
• Updated Figure 122.............................................................................................................................................................. 33
2
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